Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

[u-boot.git] / drivers / ddr / fsl / mpc85xx_ddr_gen3.c

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 1bfb9d4097ced8f0bb1f604649a1773b554fe0e0..b0a61fa2b4162d7644a88aa84ca7ba38e8db9c29 100644 (file)
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -1,13 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2008-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0
+ * Copyright 2008-2020 Freescale Semiconductor, Inc.
  */
 
-#include <common.h>
+#include <config.h>
+#include <log.h>
 #include <asm/io.h>
+#include <asm/ppc.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/processor.h>
+#include <linux/delay.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -32,29 +34,38 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        int timeout;
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
        int timeout_save;
-       volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
+       volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85xx_ECM_ADDR;
        unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
        int csn = -1;
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
        u32 save1, save2;
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
+       (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
+       defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_A008109)
+       u32 val32;
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       unsigned int ddr_freq;
+#endif
 
        switch (ctrl_num) {
        case 0:
-               ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
                break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
        case 1:
-               ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
        case 2:
-               ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
        case 3:
                ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
                break;
@@ -152,7 +163,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        if (is_warm_boot()) {
                out_be32(&ddr->sdram_cfg_2,
                         regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
-               out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+               out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
                out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 
                /* DRAM VRef will not be trained */
@@ -337,6 +348,49 @@ step2:
 
        }
 #endif
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
+       /* Erratum applies when accumulated ECC is used, or DBI is enabled */
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+       if (has_erratum_a008378()) {
+               if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+                   IS_DBI(regs->ddr_sdram_cfg_3)) {
+                       val32 = ddr_in32(&ddr->debug[28]);
+                       val32 |= (0x9 << 20);
+                       ddr_out32(&ddr->debug[28], val32);
+               }
+               debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
+       }
+#endif
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
+       val32 = in_be32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
+       out_be32(&ddr->sdram_cfg_2, val32);
+
+       val32 = in_be32(&ddr->debug[18]) | 0x2;
+       out_be32(&ddr->debug[18], val32);
+
+       out_be32(&ddr->debug[28], 0x30000000);
+       debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+       val32 = in_be32(&ddr->debug[28]);
+       val32 &= 0xff0fff00;
+       if (ddr_freq <= 1333)
+               val32 |= 0x0080006a;
+       else if (ddr_freq <= 1600)
+               val32 |= 0x0070006f;
+       else if (ddr_freq <= 1867)
+               val32 |= 0x00700076;
+       else if (ddr_freq <= 2133)
+               val32 |= 0x0060007b;
+
+       out_be32(&ddr->debug[28], val32);
+       debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
+#endif
        /*
         * For 8572 DDR1 erratum - DDR controller may enter illegal state
         * when operatiing in 32-bit bus mode with 4-beat bursts,