nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig

[u-boot.git] / include / configs / UCP1020.h

diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index c3cc72e13f7f6e871746195c721c0bdfce432507..51083569a88d432a0f4957412a660e5498d806cd 100644 (file)
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -149,7 +149,6 @@
 #define CONFIG_LBA48
 
 #define CONFIG_SYS_CLK_FREQ    66666666
-#define CONFIG_DDR_CLK_FREQ    66666666
 
 #define CONFIG_HWCONFIG
 
@@ -171,11 +170,6 @@
 #endif
 
 /* DDR Setup */
-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif
 #define CONFIG_SYS_SPD_BUS_NUM 1
 
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_512M
@@ -204,11 +198,7 @@
 #define CONFIG_SYS_DDR_SR_CNTR         0x00000000
 #define CONFIG_SYS_DDR_RCW_1           0x00000000
 #define CONFIG_SYS_DDR_RCW_2           0x00000000
-#ifdef CONFIG_DDR_ECC_ENABLE
 #define CONFIG_SYS_DDR_CONTROL         0xE70C0000      /* Type = DDR3 & ECC */
-#else
-#define CONFIG_SYS_DDR_CONTROL         0xC70C0000      /* Type = DDR3 */
-#endif
 #define CONFIG_SYS_DDR_CONTROL_2       0x04401050
 #define CONFIG_SYS_DDR_TIMING_4                0x00220001
 #define CONFIG_SYS_DDR_TIMING_5                0x03402400
@@ -310,14 +300,6 @@
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR + 0x4600)
 
 /* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED       400000
-#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED      400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
 #define CONFIG_SYS_SPD_BUS_NUM         1 /* For rom_loc and flash bank */