common: Drop log.h from common header

[u-boot.git] / drivers / mmc / socfpga_dw_mmc.c

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 759686ccd63ec082c66acda7a923548c29509b6d..892222d27da9ec913b7cc5a4abab6fbad1e114a2 100644 (file)
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -1,27 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <log.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/system_manager.h>
+#include <clk.h>
 #include <dm.h>
 #include <dwmmc.h>
 #include <errno.h>
 #include <fdtdec.h>
-#include <libfdt.h>
+#include <dm/device_compat.h>
+#include <linux/libfdt.h>
 #include <linux/err.h>
 #include <malloc.h>
+#include <reset.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-               (void *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
-               (void *)SOCFPGA_SYSMGR_ADDRESS;
-
 struct socfpga_dwmci_plat {
        struct mmc_config cfg;
        struct mmc mmc;
@@ -34,6 +32,20 @@ struct dwmci_socfpga_priv_data {
        unsigned int            smplsel;
 };
 
+static void socfpga_dwmci_reset(struct udevice *dev)
+{
+       struct reset_ctl_bulk reset_bulk;
+       int ret;
+
+       ret = reset_get_bulk(dev, &reset_bulk);
+       if (ret) {
+               dev_warn(dev, "Can't get reset: %d\n", ret);
+               return;
+       }
+
+       reset_deassert_bulk(&reset_bulk);
+}
+
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
        struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -41,35 +53,54 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
                         ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
        /* Disable SDMMC clock. */
-       clrbits_le32(&clock_manager_base->per_pll.en,
-               CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+                    CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
        debug("%s: drvsel %d smplsel %d\n", __func__,
              priv->drvsel, priv->smplsel);
-       writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
+       writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
 
        debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
-               readl(&system_manager_base->sdmmcgrp_ctrl));
+               readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
 
        /* Enable SDMMC clock */
-       setbits_le32(&clock_manager_base->per_pll.en,
-               CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+                    CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 }
 
-static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
+static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
 {
-       /* FIXME: probe from DT eventually too/ */
-       const unsigned long clk = cm_get_mmc_controller_clk_hz();
-
        struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
        struct dwmci_host *host = &priv->host;
-       int fifo_depth;
+#if CONFIG_IS_ENABLED(CLK)
+       struct clk clk;
+       int ret;
 
-       if (clk == 0) {
+       ret = clk_get_by_index(dev, 1, &clk);
+       if (ret)
+               return ret;
+
+       host->bus_hz = clk_get_rate(&clk);
+
+       clk_free(&clk);
+#else
+       /* Fixed clock divide by 4 which due to the SDMMC wrapper */
+       host->bus_hz = cm_get_mmc_controller_clk_hz();
+#endif
+       if (host->bus_hz == 0) {
                printf("DWMMC: MMC clock is zero!");
                return -EINVAL;
        }
 
+       return 0;
+}
+
+static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
+{
+       struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+       struct dwmci_host *host = &priv->host;
+       int fifo_depth;
+
        fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
                                    "fifo-depth", 0);
        if (fifo_depth < 0) {
@@ -88,8 +119,6 @@ static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
         * We only have one dwmmc block on gen5 SoCFPGA.
         */
        host->dev_index = 0;
-       /* Fixed clock divide by 4 which due to the SDMMC wrapper */
-       host->bus_hz = clk;
        host->fifoth_val = MSIZE(0x2) |
                RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
        priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
@@ -109,12 +138,18 @@ static int socfpga_dwmmc_probe(struct udevice *dev)
        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
        struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
        struct dwmci_host *host = &priv->host;
+       int ret;
+
+       ret = socfpga_dwmmc_get_clk_rate(dev);
+       if (ret)
+               return ret;
+
+       socfpga_dwmci_reset(dev);
 
 #ifdef CONFIG_BLK
        dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
        host->mmc = &plat->mmc;
 #else
-       int ret;
 
        ret = add_dwmci(host, host->bus_hz, 400000);
        if (ret)
@@ -124,7 +159,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev)
        upriv->mmc = host->mmc;
        host->mmc->dev = dev;
 
-       return 0;
+       return dwmci_probe(dev);
 }
 
 static int socfpga_dwmmc_bind(struct udevice *dev)