rename CFG_ENV_IS_NOWHERE in CONFIG_ENV_IS_NOWHERE

[u-boot.git] / include / configs / MPC8610HPCD.h

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 39201474e91ee1cee16624860daeb52c4fc45f4b..2ee8d57015f2cbc0a8fee8002c7025d25c2731c4 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -8,7 +8,6 @@
 
 /*
  * MPC8610HPCD board configuration file
- *
  */
 
 #ifndef __CONFIG_H
@@ -24,7 +23,7 @@
 #define CONFIG_FSL_DIU_FB      1       /* FSL DIU */
 
 /* video */
-#define CONFIG_VIDEO
+#undef CONFIG_VIDEO
 
 #if defined(CONFIG_VIDEO)
 #define CONFIG_CFB_CONSOLE
@@ -45,16 +44,9 @@
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SPD_EEPROM              /* Use SPD for DDR */
-#undef CONFIG_DDR_DLL                  /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
-#undef  CONFIG_DDR_ECC                 /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
-#define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_INTERRUPTS              /* enable pci, srio, ddr interrupts */
 
+#define CONFIG_HIGH_BATS       1       /* High BATs supported & enabled */
 #define CONFIG_ALTIVEC         1
 
 /*
@@ -71,10 +63,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
 #define CONFIG_MISC_INIT_R             1
 
-#undef CFG_DRAM_TEST                   /* memory test, takes time */
 #define CFG_MEMTEST_START      0x00200000      /* memtest region */
 #define CFG_MEMTEST_END                0x00400000
-#define CFG_ALT_MEMTEST
 
 /*
  * Base addresses -- Note these are effective addresses where the
@@ -90,31 +80,34 @@
 
 #define CFG_DIU_ADDR           (CFG_CCSRBAR+0x2c000)
 
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM              /* Use SPD for DDR */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE  0xDeadBeef
+
 #define CFG_DDR_SDRAM_BASE     0x00000000      /* DDR is system memory*/
 #define CFG_SDRAM_BASE         CFG_DDR_SDRAM_BASE
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS1            0x51            /* DDR DIMM */
-#else
-/*
- * Manually set up DDR1 parameters
- */
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
 
+/* These are used when DDR doesn't use SPD.  */
 #define CFG_SDRAM_SIZE 256             /* DDR is 256MB */
 
 #if 0 /* TODO */
 #define CFG_DDR_CS0_BNDS       0x0000000F
 #define CFG_DDR_CS0_CONFIG     0x80010202      /* Enable, no interleaving */
-#define CFG_DDR_EXT_REFRESH    0x00000000
+#define CFG_DDR_TIMING_3       0x00000000
 #define CFG_DDR_TIMING_0       0x00260802
 #define CFG_DDR_TIMING_1       0x3935d322
 #define CFG_DDR_TIMING_2       0x14904cc8
@@ -131,7 +124,10 @@
 #define CFG_DDR_ERR_INT_EN     0x00000000
 #define CFG_DDR_ERR_DIS                0x00000000
 #define CFG_DDR_SBE            0x000f0000
- /* Not used in fixed_sdram function */
+
+/*
+ * FIXME: Not used in fixed_sdram function
+ */
 #define CFG_DDR_MODE           0x00000022
 #define CFG_DDR_CS1_BNDS       0x00000000
 #define CFG_DDR_CS2_BNDS       0x00000FFF      /* Not done */
@@ -139,13 +135,13 @@
 #define CFG_DDR_CS4_BNDS       0x00000FFF      /* Not done */
 #define CFG_DDR_CS5_BNDS       0x00000FFF      /* Not done */
 #endif
-#endif
 
-#define CFG_ID_EEPROM
-#ifdef CFG_ID_EEPROM
+
 #define CONFIG_ID_EEPROM
-#endif
-#define ID_EEPROM_ADDR         0x57
+#define CFG_I2C_EEPROM_NXID
+#define CONFIG_ID_EEPROM
+#define CFG_I2C_EEPROM_ADDR     0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
 
 
 #define CFG_FLASH_BASE         0xf0000000 /* start of FLASH 128M */
@@ -193,7 +189,7 @@
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (ms) */
 #define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor */
 
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
@@ -330,7 +326,7 @@
 #define CONFIG_USB_KEYBOARD    1
 #define CFG_DEVICE_DEREGISTER
 #define CFG_USB_EVENT_POLL     1
-#define CFG_USB_OHCI_SLOT_NAME         "ohci_pci"
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 #define CFG_OHCI_SWAP_REG_ACCESS       1
 
@@ -447,7 +443,7 @@
 #define CFG_ENV_SECT_SIZE      0x20000 /* 126k (one sector) for env */
 #define CFG_ENV_SIZE           0x2000
 #else
-#define CFG_ENV_IS_NOWHERE     1       /* Store ENV in memory only */
+#define CONFIG_ENV_IS_NOWHERE  1       /* Store ENV in memory only */
 #define CFG_ENV_ADDR           (CFG_MONITOR_BASE - 0x1000)
 #define CFG_ENV_SIZE           0x2000
 #endif
@@ -486,7 +482,8 @@
 #endif
 
 
-#undef CONFIG_WATCHDOG                 /* watchdog disabled */
+#define CONFIG_WATCHDOG                        /* watchdog enabled */
+#define CFG_WATCHDOG_FREQ      5000    /* Feed interval, 5s */
 
 /*DIU Configuration*/
 #define DIU_CONNECT_TO_DVI             /* DIU controller connects to DVI encoder*/