#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <div64.h>
#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
+static u32 get_root_clk(enum clk_root_index clock_id);
+
+#ifdef CONFIG_IMX_HAB
+void hab_caam_clock_enable(unsigned char enable)
+{
+ /* The CAAM clock is always on for iMX8M */
+}
+#endif
+
void enable_ocotp_clk(unsigned char enable)
{
clock_enable(CCGR_OCOTP, !!enable);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
- /* 0 - 3 is valid i2c num */
- if (i2c_num > 3)
+ u8 i2c_ccgr[] = {
+ CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4,
+#if (IS_ENABLED(CONFIG_IMX8MP))
+ CCGR_I2C5_8MP, CCGR_I2C6_8MP
+#endif
+ };
+
+ if (i2c_num >= ARRAY_SIZE(i2c_ccgr))
return -EINVAL;
- clock_enable(CCGR_I2C1 + i2c_num, !!enable);
+ clock_enable(i2c_ccgr[i2c_num], !!enable);
return 0;
}
#ifdef CONFIG_SPL_BUILD
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
+ PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
- PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
+ PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
};
}
if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
- printf("No matched freq table %u\n", freq);
+ printf("%s: No matched freq table %u\n", __func__, freq);
return -EINVAL;
}
case ANATOP_DRAM_PLL:
setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
- writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
pll_base = &ana_pll->dram_pll_gnrl_ctl;
break;
}
if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
- printf("No matched freq table %lu\n", clk_val);
+ printf("%s: No matched freq table %lu\n", __func__, clk_val);
return;
}
}
#endif
+int intpll_configure(enum pll_clocks pll, ulong freq)
+{
+ void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
+ u32 pll_div_ctl_val, pll_clke_masks;
+
+ switch (pll) {
+ case ANATOP_SYSTEM_PLL1:
+ pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
+ pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
+ pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
+ INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
+ INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
+ INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
+ INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_SYSTEM_PLL2:
+ pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
+ pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
+ pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
+ INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
+ INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
+ INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
+ INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_SYSTEM_PLL3:
+ pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
+ pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_ARM_PLL:
+ pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
+ pll_div_ctl = &ana_pll->arm_pll_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_GPU_PLL:
+ pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
+ pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ case ANATOP_VPU_PLL:
+ pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
+ pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
+ pll_clke_masks = INTPLL_CLKE_MASK;
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ switch (freq) {
+ case MHZ(600):
+ /* 24 * 0x12c / 3 / 2 ^ 2 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
+ break;
+ case MHZ(750):
+ /* 24 * 0xfa / 2 / 2 ^ 2 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+ INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
+ break;
+ case MHZ(800):
+ /* 24 * 0x190 / 3 / 2 ^ 2 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
+ break;
+ case MHZ(1000):
+ /* 24 * 0xfa / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1200):
+ /* 24 * 0x12c / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1400):
+ /* 24 * 0x15e / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1500):
+ /* 24 * 0x177 / 3 / 2 ^ 1 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
+ break;
+ case MHZ(1600):
+ /* 24 * 0xc8 / 3 / 2 ^ 0 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+ break;
+ case MHZ(1800):
+ /* 24 * 0xe1 / 3 / 2 ^ 0 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+ break;
+ case MHZ(2000):
+ /* 24 * 0xfa / 3 / 2 ^ 0 */
+ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
+ INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
+ break;
+ default:
+ return -EINVAL;
+ };
+ /* Bypass clock and set lock to pll output lock */
+ setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
+ /* Enable reset */
+ clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
+ /* Configure */
+ writel(pll_div_ctl_val, pll_div_ctl);
+
+ __udelay(100);
+
+ /* Disable reset */
+ setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
+ /* Wait Lock */
+ while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
+ ;
+ /* Clear bypass */
+ clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
+ setbits_le32(pll_gnrl_ctl, pll_clke_masks);
+
+ return 0;
+}
+
void init_uart_clk(u32 index)
{
/*
clock_enable(CCGR_WDOG3, 1);
}
+void init_clk_usdhc(u32 index)
+{
+ /*
+ * set usdhc clock root
+ * sys pll1 400M
+ */
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_USDHC1, 0);
+ clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_USDHC1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_USDHC2, 0);
+ clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_USDHC2, 1);
+ return;
+ case 2:
+ clock_enable(CCGR_USDHC3, 0);
+ clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_USDHC3, 1);
+ return;
+ default:
+ printf("Invalid usdhc index\n");
+ return;
+ }
+}
+
+void init_clk_ecspi(u32 index)
+{
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_ECSPI1, 0);
+ clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_ECSPI1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_ECSPI2, 0);
+ clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_ECSPI2, 1);
+ return;
+ case 2:
+ clock_enable(CCGR_ECSPI3, 0);
+ clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_ECSPI3, 1);
+ return;
+ default:
+ printf("Invalid ecspi index\n");
+ return;
+ }
+}
+
+void init_nand_clk(void)
+{
+ /*
+ * set rawnand root
+ * sys pll1 400M
+ */
+ clock_enable(CCGR_RAWNAND, 0);
+ clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
+ clock_enable(CCGR_RAWNAND, 1);
+}
+
int clock_init(void)
{
u32 val_cfg0;
INTPLL_DIV20_CLKE_MASK;
writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
+ /* Configure ARM at 1.2GHz */
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(2));
+
+ intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
+
+ /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
+ clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
+
+ if (is_imx8mn() || is_imx8mp())
+ intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
+ else
+ intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
+
+#ifdef CONFIG_IMX8MP
+ /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
+ /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
+ clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
+#else
+ clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
+
/* config GIC to sys_pll2_100m */
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(3));
clock_enable(CCGR_GIC, 1);
+#endif
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
break;
default:
- printf("Not supported\n");
+ printf("Unsupported clk_root_src %d\n", frac_pll);
return 0;
}
/* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
- if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
+ if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
return 0;
- if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
+ if ((pll_gnrl_ctl & RST_MASK) == 0)
return 0;
/*
* When BYPASS is equal to 1, PLL enters the bypass mode
* regardless of the values of RESETB
*/
- if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
+ if (pll_gnrl_ctl & BYPASS_MASK)
return 24000000u;
- if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
+ if (!(pll_gnrl_ctl & LOCK_STATUS)) {
puts("pll not locked\n");
return 0;
}
- if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
+ if (!(pll_gnrl_ctl & CLKE_MASK))
return 0;
- main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
- INTPLL_MAIN_DIV_SHIFT;
- pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
- INTPLL_PRE_DIV_SHIFT;
- post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
- INTPLL_POST_DIV_SHIFT;
+ main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
+ MDIV_SHIFT;
+ pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
+ PDIV_SHIFT;
+ post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
+ SDIV_SHIFT;
- k = pll_fdiv_ctl1 & GENMASK(15, 0);
+ k = pll_fdiv_ctl1 & KDIV_MASK;
return lldiv((main_div * 65536 + k) * 24000000ULL,
65536 * pre_div * (1 << post_div));
case AUDIO_PLL2_CLK:
case VIDEO_PLL_CLK:
return decode_fracpll(root_src);
+ case ARM_A53_ALT_CLK:
+ return get_root_clk(ARM_A53_CLK_ROOT);
default:
return 0;
}
return root_src_clk / (post_podf + 1) / (pre_podf + 1);
}
+u32 get_arm_core_clk(void)
+{
+ enum clk_root_src root_src;
+ u32 root_src_clk;
+
+ if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ return root_src_clk;
+}
+
u32 mxc_get_clock(enum mxc_clock clk)
{
u32 val;
switch (clk) {
case MXC_ARM_CLK:
- return get_root_clk(ARM_A53_CLK_ROOT);
+ return get_arm_core_clk();
case MXC_IPG_CLK:
clock_get_target_val(IPG_CLK_ROOT, &val);
val = val & 0x3;
return 0;
}
+
+#if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS)
+static int imx8mp_eqos_interface_init(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ clrbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_MII:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#else
+static int imx8mp_eqos_interface_init(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int imx8mp_fec_interface_init(struct udevice *dev,
+ phy_interface_t interface_type,
+ bool mx8mp)
+{
+ /* i.MX8MP has extra RGMII_EN bit in IOMUXC GPR1 register */
+ const u32 rgmii_en = mx8mp ? IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN : 0;
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ clrbits_le32(&gpr->gpr[1],
+ rgmii_en |
+ IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_RMII:
+ setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ setbits_le32(&gpr->gpr[1], rgmii_en);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#else
+static int imx8mp_fec_interface_init(struct udevice *dev,
+ phy_interface_t interface_type,
+ bool mx8mp)
+{
+ return 0;
+}
+#endif
+
+int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
+{
+ if (IS_ENABLED(CONFIG_IMX8MM) &&
+ IS_ENABLED(CONFIG_FEC_MXC) &&
+ device_is_compatible(dev, "fsl,imx8mm-fec"))
+ return imx8mp_fec_interface_init(dev, interface_type, false);
+
+ if (IS_ENABLED(CONFIG_IMX8MN) &&
+ IS_ENABLED(CONFIG_FEC_MXC) &&
+ device_is_compatible(dev, "fsl,imx8mn-fec"))
+ return imx8mp_fec_interface_init(dev, interface_type, false);
+
+ if (IS_ENABLED(CONFIG_IMX8MP) &&
+ IS_ENABLED(CONFIG_FEC_MXC) &&
+ device_is_compatible(dev, "fsl,imx8mp-fec"))
+ return imx8mp_fec_interface_init(dev, interface_type, true);
+
+ if (IS_ENABLED(CONFIG_IMX8MP) &&
+ IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
+ device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))
+ return imx8mp_eqos_interface_init(dev, interface_type);
+
+ return -EINVAL;
+}
projects / u-boot.git / blobdiff