global: Make <asm/global_data.h> include <asm/u-boot.h>

[u-boot.git] / arch / arm / mach-socfpga / spl_a10.c

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index b5f43f09d190d735f01e29299b1c9f0ccc0aa65b..c20376f7f8ef3029293cda16f57f09e6f9a9c628 100644 (file)
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -1,16 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 // SPDX-License-Identifier: GPL-2.0+
 /*

- *  Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2021 Altera Corporation <www.altera.com>

  */
 
  */
 

-#include <common.h>
+#include <config.h>

 #include <cpu_func.h>
 #include <hang.h>
 #include <init.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/pl310.h>
 #include <cpu_func.h>
 #include <hang.h>
 #include <init.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/pl310.h>

-#include <asm/u-boot.h>

 #include <asm/utils.h>
 #include <image.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/utils.h>
 #include <image.h>
 #include <asm/arch/reset_manager.h>


@@ -30,13 +29,18 @@
 #include <asm/arch/fpga_manager.h>
 #include <mmc.h>
 #include <memalign.h>
 #include <asm/arch/fpga_manager.h>
 #include <mmc.h>
 #include <memalign.h>

+#include <linux/delay.h>

 
 #define FPGA_BUFSIZ    16 * 1024
 
 #define FPGA_BUFSIZ    16 * 1024

+#define FSBL_IMAGE_IS_VALID    0x49535756
+
+#define FSBL_IMAGE_IS_INVALID  0x0
+#define BOOTROM_CONFIGURES_IO_PINMUX   0x3

 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BOOTROM_SHARED_MEM_SIZE                0x800   /* 2KB */
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BOOTROM_SHARED_MEM_SIZE                0x800   /* 2KB */

-#define BOOTROM_SHARED_MEM_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
+#define BOOTROM_SHARED_MEM_ADDR                (CFG_SYS_INIT_RAM_ADDR + \

                                         SOCFPGA_PHYS_OCRAM_SIZE - \
                                         BOOTROM_SHARED_MEM_SIZE)
 #define RST_STATUS_SHARED_ADDR         (BOOTROM_SHARED_MEM_ADDR + 0x438)
                                         SOCFPGA_PHYS_OCRAM_SIZE - \
                                         BOOTROM_SHARED_MEM_SIZE)
 #define RST_STATUS_SHARED_ADDR         (BOOTROM_SHARED_MEM_ADDR + 0x438)


@@ -93,8 +97,8 @@ u32 spl_boot_device(void)
        }
 }
 
        }
 }
 

-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_mmc_boot_mode(const u32 boot_device)
+#ifdef CONFIG_SPL_MMC
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

 {
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
        return MMCSD_MODE_FS;
 {
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
        return MMCSD_MODE_FS;


@@ -106,32 +110,136 @@ u32 spl_mmc_boot_mode(const u32 boot_device)
 
 void spl_board_init(void)
 {
 
 void spl_board_init(void)
 {

+       int ret;
+

        ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
 
        /* enable console uart printing */
        preloader_console_init();
        ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
 
        /* enable console uart printing */
        preloader_console_init();

-       WATCHDOG_RESET();
+       schedule();

 
        arch_early_init_r();
 
        /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
 
        arch_early_init_r();
 
        /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */

-       if (is_fpgamgr_user_mode()) {
-               int ret = config_pins(gd->fdt_blob, "shared");
-
+       if ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
+            is_regular_boot_valid()) ||
+           (!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
+            is_fpgamgr_user_mode())) {
+               ret = config_pins(gd->fdt_blob, "shared");

                if (ret)
                        return;
 
                ret = config_pins(gd->fdt_blob, "fpga");
                if (ret)
                        return;
                if (ret)
                        return;
 
                ret = config_pins(gd->fdt_blob, "fpga");
                if (ret)
                        return;

-       } else if (!is_fpgamgr_early_user_mode()) {
+       } else if (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) ||
+                  !is_fpgamgr_early_user_mode()) {

                /* Program IOSSM(early IO release) or full FPGA */
                fpgamgr_program(buf, FPGA_BUFSIZ, 0);
                /* Program IOSSM(early IO release) or full FPGA */
                fpgamgr_program(buf, FPGA_BUFSIZ, 0);

+
+               /* Skipping double program for combined RBF */
+               if (!is_fpgamgr_user_mode()) {
+                       /*
+                        * Expect FPGA entered early user mode, so
+                        * the flag is set to re-program IOSSM
+                        */
+                       force_periph_program(true);
+
+                       /* Re-program IOSSM to stabilize IO system */
+                       fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+
+                       force_periph_program(false);
+               }

        }
 
        /* If the IOSSM/full FPGA is already loaded, start DDR */
        }
 
        /* If the IOSSM/full FPGA is already loaded, start DDR */

-       if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+       if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) {
+               if (!is_regular_boot_valid()) {
+                       /*
+                        * Ensure all signals in stable state before triggering
+                        * warm reset. This value is recommended from stress
+                        * test.
+                        */
+                       mdelay(10);
+
+#if IS_ENABLED(CONFIG_CADENCE_QSPI)
+                       /*
+                        * Trigger software reset to QSPI flash.
+                        * On some boards, the QSPI flash reset may not be
+                        * connected to the HPS warm reset.
+                        */
+                       qspi_flash_software_reset();
+#endif
+
+                       ret = readl(socfpga_get_rstmgr_addr() +
+                                   RSTMGR_A10_SYSWARMMASK);
+                       /*
+                        * Masking s2f & FPGA manager module reset from warm
+                        * reset
+                        */
+                       writel(ret & (~(ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
+                              ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK)),
+                              socfpga_get_rstmgr_addr() +
+                              RSTMGR_A10_SYSWARMMASK);
+
+                       /*
+                        * BootROM will configure both IO and pin mux after a
+                        * warm reset
+                        */
+                       ret = readl(socfpga_get_sysmgr_addr() +
+                                   SYSMGR_A10_ROMCODE_CTRL);
+                       writel(ret | BOOTROM_CONFIGURES_IO_PINMUX,
+                              socfpga_get_sysmgr_addr() +
+                              SYSMGR_A10_ROMCODE_CTRL);
+
+                       /*
+                        * Up to here, image is considered valid and should be
+                        * set as valid before warm reset is triggered
+                        */
+                       writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
+                              SYSMGR_A10_ROMCODE_INITSWSTATE);
+
+                       /*
+                        * Set this flag to scratch register, so that a proper
+                        * boot progress before / after warm reset can be
+                        * tracked by FSBL
+                        */
+                       set_regular_boot(true);
+
+                       schedule();
+
+                       reset_cpu();
+               }
+
+               /*
+                * Reset this flag to scratch register, so that a proper
+                * boot progress before / after warm reset can be
+                * tracked by FSBL
+                */
+               set_regular_boot(false);
+
+               ret = readl(socfpga_get_rstmgr_addr() +
+                           RSTMGR_A10_SYSWARMMASK);
+
+               /*
+                * Unmasking s2f & FPGA manager module reset from warm
+                * reset
+                */
+               writel(ret | ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
+                       ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK,
+                       socfpga_get_rstmgr_addr() + RSTMGR_A10_SYSWARMMASK);
+
+               /*
+                * Up to here, MPFE hang workaround is considered done and
+                * should be reset as invalid until FSBL successfully loading
+                * SSBL, and prepare jumping to SSBL, then only setting as
+                * valid
+                */
+               writel(FSBL_IMAGE_IS_INVALID, socfpga_get_sysmgr_addr() +
+                      SYSMGR_A10_ROMCODE_INITSWSTATE);
+

                ddr_calibration_sequence();
                ddr_calibration_sequence();

+       }

 
        if (!is_fpgamgr_user_mode())
                fpgamgr_program(buf, FPGA_BUFSIZ, 0);
 
        if (!is_fpgamgr_user_mode())
                fpgamgr_program(buf, FPGA_BUFSIZ, 0);


@@ -163,9 +271,16 @@ void board_init_f(ulong dummy)
 
        /* reconfigure and enable the watchdog */
        hw_watchdog_init();
 
        /* reconfigure and enable the watchdog */
        hw_watchdog_init();

-       WATCHDOG_RESET();
+       schedule();

 #endif /* CONFIG_HW_WATCHDOG */
 
        config_dedicated_pins(gd->fdt_blob);
 #endif /* CONFIG_HW_WATCHDOG */
 
        config_dedicated_pins(gd->fdt_blob);

-       WATCHDOG_RESET();
+       schedule();
+}
+
+/* board specific function prior loading SSBL / U-Boot proper */
+void spl_board_prepare_for_boot(void)
+{
+       writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
+              SYSMGR_A10_ROMCODE_INITSWSTATE);

 }
 }