/**
* struct xilinx_pcie - Xilinx PCIe controller state
- * @hose: The parent classes PCI controller state
* @cfg_base: The base address of memory mapped configuration space
*/
struct xilinx_pcie {
- struct pci_controller hose;
void *cfg_base;
};
/**
* pcie_xilinx_read_config() - Read from configuration space
- * @pcie: Pointer to the PCI controller state
+ * @bus: Pointer to the PCI bus
* @bdf: Identifies the PCIe device to access
* @offset: The offset into the device's configuration space
* @valuep: A pointer at which to store the read value
/**
* pcie_xilinx_write_config() - Write to configuration space
- * @pcie: Pointer to the PCI controller state
+ * @bus: Pointer to the PCI bus
* @bdf: Identifies the PCIe device to access
* @offset: The offset into the device's configuration space
* @value: The value to write
DECLARE_GLOBAL_DATA_PTR;
int err;
- err = fdt_get_resource(gd->fdt_blob, dev->of_offset, "reg",
+ err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
0, ®_res);
if (err < 0) {
- error("\"reg\" resource not found\n");
+ pr_err("\"reg\" resource not found\n");
return err;
}