fsl_ddr: Move DDR config options to driver Kconfig
[u-boot.git] / arch / arm / cpu / armv7 / ls102xa / Kconfig
index d154f7b0f68c8b4d9066e2bef326b1a4c483b3d8..eca1d06ca5dcbfc68298c2e08817c034174467fc 100644 (file)
@@ -3,8 +3,10 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
-       select SYS_FSL_DDR_BE
-       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_DDR_BE if SYS_FSL_DDR
+       select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+       select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+       select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
@@ -49,47 +51,6 @@ config SYS_FSL_SRDS_2
 config SYS_HAS_SERDES
        bool
 
-config SYS_FSL_DDR
-       bool "Freescale DDR driver"
-       help
-         Select Freescale General DDR driver, shared between most Freescale
-         PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-         based Layerscape SoCs (such as ls2080a).
-
-config SYS_FSL_DDR_BE
-       bool
-       default y
-       help
-         Access DDR registers in big-endian.
-
-config SYS_FSL_DDR_VER
-       int
-       default 50 if SYS_FSL_DDR_VER_50
-
-config SYS_FSL_DDR_VER_50
-       bool
-
-config SYS_FSL_DDRC_ARM_GEN3
-       bool
-
-config SYS_FSL_DDRC_GEN4
-       bool
-
-config SYS_FSL_DDR3
-       bool "Freescale DDR3 controller"
-       depends on !SYS_FSL_DDR4
-       select SYS_FSL_DDR
-       select SYS_FSL_DDRC_ARM_GEN3
-       help
-         Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-       bool "Freescale DDR4 controller"
-       select SYS_FSL_DDR
-       select SYS_FSL_DDRC_GEN4
-       help
-         Enable Freescale DDR4 controller.
-
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
        depends on ARCH_LS1021A
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