*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
#define CONFIG_HOSTNAME rainier
#endif
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
* Define this if you want support for video console with radeon 9200 pci card
* Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
*/
-#undef CONFIG_VIDEO
#ifdef CONFIG_VIDEO
/*
#define CONFIG_4xx_DCACHE /* enable dcache */
#endif
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
/*
/*
* Environment
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
-#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
-#elif defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
#define CONFIG_ENV_SIZE (8 << 10)
-/*
- * In RAM-booting version, we have no environment storage. So we need to
- * provide at least preliminary MAC addresses for the 4xx EMAC driver to
- * register the interfaces. Those two addresses are generated via the
- * tools/gen_eth_addr tool and should only be used in a closed laboratory
- * environment.
- */
-#define CONFIG_ETHADDR 4a:56:49:22:3e:43
-#define CONFIG_ETH1ADDR 02:93:53:d5:06:98
#else
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
#endif
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+#endif /* CONFIG_CMD_FLASH */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
-#endif /* CONFIG_CMD_FLASH */
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller. sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
- /* this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
/*
* DDR SDRAM
*/
#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/*
* I2C
*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_AD7414 1 /* use AD7414 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
/*
* Default environment variables
*/
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_PPC_OLD \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
- CONFIG_AMCC_DEF_ENV_NAND_UPD \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
""
/* USB */
#ifdef CONFIG_440EPX
-
-#undef CONFIG_USB_EHCI /* OHCI by default */
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_EHCI_PPC4XX
#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#else /* CONFIG_USB_EHCI */
+#else /* CONFIG_USB_EHCI_HCD */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#endif
-#define CONFIG_USB_STORAGE
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
#endif /* CONFIG_440EPX */
/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CHIP_CONFIG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#ifdef CONFIG_440EPX
-#define CONFIG_CMD_USB
#endif
#ifndef CONFIG_RAINIER
* overwrite part of the U-Boot image which is already loaded from NAND
* to SDRAM.
*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_POST_MEMORY_ON 0
#else
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
#define CONFIG_SUPPORT_VFAT
/*
* PCI stuff
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
- !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x03017200
#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
#define VIDEO_IO_OFFSET 0xe8000000
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
-#define CONFIG_CFB_CONSOLE
#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CMD_BMP
#endif
#endif /* __CONFIG_H */
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