#include <common.h>
#include <mpc5xxx.h>
+#include <pci.h>
-long int initdram (int board_type)
-{
#ifndef CFG_RAMBOOT
- /* configure SDRAM start/end */
-#if defined(CONFIG_MPC5200)
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x00000018;/* 32M at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x02000000;/* disabled */
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+#ifdef CONFIG_MPC5200_DDR
/* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit;
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000;
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000;
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
/* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit;
/* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000;
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit;
+#else
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
+ /* set mode register */
+#if defined(CONFIG_MPC5200)
+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
+#elif defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+#endif
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
/* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
+#endif
+}
+#endif
+
+long int initdram (int board_type)
+{
+ ulong dramsize = 0;
+#ifdef CONFIG_MPC5200_DDR
+ ulong dramsize2 = 0;
+#endif
+#ifndef CFG_RAMBOOT
+ ulong test1, test2;
+
+ /* configure SDRAM start/end */
+#if defined(CONFIG_MPC5200)
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+
+#ifdef CONFIG_MPC5200_DDR
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
+
+ /* set tap delay to 0x10 */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
+#else
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xd2322800;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x8ad70000;
+#endif
+
#elif defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
- *(vu_long *)MPC5XXX_SDRAM_STOP = 0x000007ff;/* 64M */
+ *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
/* setup config registers */
/* address select register */
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0000;
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002;
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0004;
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x514f0000;
#endif
+ sdram_start(0);
+ test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+#if defined(CONFIG_MPC5200)
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG =
+ (0x13 + __builtin_ffs(dramsize >> 20) - 1);
+#ifdef CONFIG_MPC5200_DDR
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+ sdram_start(0);
+ test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG =
+ dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
#else
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#endif
+#elif defined(CONFIG_MGT5100)
+ *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+#endif
+
+#else /* CFG_RAMBOOT */
#ifdef CONFIG_MGT5100
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+ dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+#else
+ dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
+#ifdef CONFIG_MPC5200_DDR
+ dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
#endif
#endif
- /* return total ram size */
-#if defined(CONFIG_MGT5100)
- return (64 * 1024 * 1024);
-#elif defined(CONFIG_MPC5200)
- return (32 * 1024 * 1024);
+#endif /* CFG_RAMBOOT */
+
+#ifdef CONFIG_MPC5200_DDR
+ dramsize += dramsize2;
#endif
+ /* return total ram size */
+ return dramsize;
}
int checkboard (void)
#endif
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x800000) { /* adjust mapping */
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ START_REG(CFG_BOOTCS_START | size);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ STOP_REG(CFG_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4 0x01000000UL
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ }
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
projects / u-boot.git / blobdiff