Subtree merge tag 'v6.11-dts' of dts repo [1] into dts/upstream

[u-boot.git] / dts / upstream / src / riscv / starfive / jh7110.dtsi

diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi b/dts/upstream/src/riscv/starfive/jh7110.dtsi
index 18047195c600bdca0f98ac64337d79e91ce202ab..0d8339357bad32f95ffa0396e9a7cea328d705ff 100644 (file)
--- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
@@ -387,12 +387,13 @@
                };
 
                uart0: serial@10000000 {
-                       compatible = "snps,dw-apb-uart";
+                       compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
                        reg = <0x0 0x10000000 0x0 0x10000>;
                        clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
                                 <&syscrg JH7110_SYSCLK_UART0_APB>;
                        clock-names = "baudclk", "apb_pclk";
-                       resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+                       resets = <&syscrg JH7110_SYSRST_UART0_APB>,
+                                <&syscrg JH7110_SYSRST_UART0_CORE>;
                        interrupts = <32>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
@@ -400,12 +401,13 @@
                };
 
                uart1: serial@10010000 {
-                       compatible = "snps,dw-apb-uart";
+                       compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
                        reg = <0x0 0x10010000 0x0 0x10000>;
                        clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
                                 <&syscrg JH7110_SYSCLK_UART1_APB>;
                        clock-names = "baudclk", "apb_pclk";
-                       resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+                       resets = <&syscrg JH7110_SYSRST_UART1_APB>,
+                                <&syscrg JH7110_SYSRST_UART1_CORE>;
                        interrupts = <33>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
@@ -413,12 +415,13 @@
                };
 
                uart2: serial@10020000 {
-                       compatible = "snps,dw-apb-uart";
+                       compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
                        reg = <0x0 0x10020000 0x0 0x10000>;
                        clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
                                 <&syscrg JH7110_SYSCLK_UART2_APB>;
                        clock-names = "baudclk", "apb_pclk";
-                       resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+                       resets = <&syscrg JH7110_SYSRST_UART2_APB>,
+                                <&syscrg JH7110_SYSRST_UART2_CORE>;
                        interrupts = <34>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
@@ -642,12 +645,13 @@
                };
 
                uart3: serial@12000000 {
-                       compatible = "snps,dw-apb-uart";
+                       compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
                        reg = <0x0 0x12000000 0x0 0x10000>;
                        clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
                                 <&syscrg JH7110_SYSCLK_UART3_APB>;
                        clock-names = "baudclk", "apb_pclk";
-                       resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+                       resets = <&syscrg JH7110_SYSRST_UART3_APB>,
+                                <&syscrg JH7110_SYSRST_UART3_CORE>;
                        interrupts = <45>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
@@ -655,12 +659,13 @@
                };
 
                uart4: serial@12010000 {
-                       compatible = "snps,dw-apb-uart";
+                       compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
                        reg = <0x0 0x12010000 0x0 0x10000>;
                        clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
                                 <&syscrg JH7110_SYSCLK_UART4_APB>;
                        clock-names = "baudclk", "apb_pclk";
-                       resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+                       resets = <&syscrg JH7110_SYSRST_UART4_APB>,
+                                <&syscrg JH7110_SYSRST_UART4_CORE>;
                        interrupts = <46>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
@@ -668,12 +673,13 @@
                };
 
                uart5: serial@12020000 {
-                       compatible = "snps,dw-apb-uart";
+                       compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
                        reg = <0x0 0x12020000 0x0 0x10000>;
                        clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
                                 <&syscrg JH7110_SYSCLK_UART5_APB>;
                        clock-names = "baudclk", "apb_pclk";
-                       resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+                       resets = <&syscrg JH7110_SYSRST_UART5_APB>,
+                                <&syscrg JH7110_SYSRST_UART5_CORE>;
                        interrupts = <47>;
                        reg-io-width = <4>;
                        reg-shift = <2>;
@@ -1214,5 +1220,91 @@
                        #reset-cells = <1>;
                        power-domains = <&pwrc JH7110_PD_VOUT>;
                };
+
+               pcie0: pcie@940000000 {
+                       compatible = "starfive,jh7110-pcie";
+                       reg = <0x9 0x40000000 0x0 0x1000000>,
+                             <0x0 0x2b000000 0x0 0x100000>;
+                       reg-names = "cfg", "apb";
+                       linux,pci-domain = <0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
+                       interrupts = <56>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
+                                       <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
+                                       <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
+                                       <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
+                       msi-controller;
+                       device_type = "pci";
+                       starfive,stg-syscon = <&stg_syscon>;
+                       bus-range = <0x0 0xff>;
+                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+                       clock-names = "noc", "tl", "axi_mst0", "apb";
+                       resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
+                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
+                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
+                                <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+                                <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+                                <&stgcrg JH7110_STGRST_PCIE0_APB>;
+                       reset-names = "mst0", "slv0", "slv", "brg",
+                                     "core", "apb";
+                       status = "disabled";
+
+                       pcie_intc0: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               pcie1: pcie@9c0000000 {
+                       compatible = "starfive,jh7110-pcie";
+                       reg = <0x9 0xc0000000 0x0 0x1000000>,
+                             <0x0 0x2c000000 0x0 0x100000>;
+                       reg-names = "cfg", "apb";
+                       linux,pci-domain = <1>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
+                       interrupts = <57>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
+                                       <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
+                                       <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
+                                       <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
+                       msi-controller;
+                       device_type = "pci";
+                       starfive,stg-syscon = <&stg_syscon>;
+                       bus-range = <0x0 0xff>;
+                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+                       clock-names = "noc", "tl", "axi_mst0", "apb";
+                       resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
+                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
+                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
+                                <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+                                <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+                                <&stgcrg JH7110_STGRST_PCIE1_APB>;
+                       reset-names = "mst0", "slv0", "slv", "brg",
+                                     "core", "apb";
+                       status = "disabled";
+
+                       pcie_intc1: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
        };
 };