Subtree merge tag 'v6.11-dts' of dts repo [1] into dts/upstream

[u-boot.git] / dts / upstream / src / arm64 / mediatek / mt7988a.dtsi

diff --git a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
index bba97de4fb4497c393a9154175a698952895f1ab..aa728331e876b7c94c8d71a94d66d792f2688cd3 100644 (file)
--- a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only OR MIT
 
+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
        compatible = "mediatek,mt7988a";
@@ -78,7 +80,7 @@
                        #interrupt-cells = <3>;
                };
 
-               clock-controller@10001000 {
+               infracfg: clock-controller@10001000 {
                        compatible = "mediatek,mt7988-infracfg", "syscon";
                        reg = <0 0x10001000 0 0x1000>;
                        #clock-cells = <1>;
@@ -103,6 +105,92 @@
                        #clock-cells = <1>;
                };
 
+               pwm@10048000 {
+                       compatible = "mediatek,mt7988-pwm";
+                       reg = <0 0x10048000 0 0x1000>;
+                       clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
+                                <&infracfg CLK_INFRA_66M_PWM_HCK>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK1>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK2>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK3>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK4>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK5>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK6>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK7>,
+                                <&infracfg CLK_INFRA_66M_PWM_CK8>;
+                       clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+                                     "pwm4", "pwm5", "pwm6", "pwm7", "pwm8";
+                       #pwm-cells = <2>;
+                       status = "disabled";
+               };
+
+               i2c@11003000 {
+                       compatible = "mediatek,mt7981-i2c";
+                       reg = <0 0x11003000 0 0x1000>,
+                             <0 0x10217080 0 0x80>;
+                       interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+                                <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c@11004000 {
+                       compatible = "mediatek,mt7981-i2c";
+                       reg = <0 0x11004000 0 0x1000>,
+                             <0 0x10217100 0 0x80>;
+                       interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+                                <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c@11005000 {
+                       compatible = "mediatek,mt7981-i2c";
+                       reg = <0 0x11005000 0 0x1000>,
+                             <0 0x10217180 0 0x80>;
+                       interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+                                <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               usb@11190000 {
+                       compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
+                       reg = <0 0x11190000 0 0x2e00>,
+                             <0 0x11193e00 0 0x0100>;
+                       reg-names = "mac", "ippc";
+                       interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&infracfg CLK_INFRA_USB_SYS>,
+                                <&infracfg CLK_INFRA_USB_REF>,
+                                <&infracfg CLK_INFRA_66M_USB_HCK>,
+                                <&infracfg CLK_INFRA_133M_USB_HCK>,
+                                <&infracfg CLK_INFRA_USB_XHCI>;
+                       clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+               };
+
+               usb@11200000 {
+                       compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
+                       reg = <0 0x11200000 0 0x2e00>,
+                             <0 0x11203e00 0 0x0100>;
+                       reg-names = "mac", "ippc";
+                       interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
+                                <&infracfg CLK_INFRA_USB_CK_P1>,
+                                <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
+                                <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
+                                <&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
+                       clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+               };
+
                clock-controller@11f40000 {
                        compatible = "mediatek,mt7988-xfi-pll";
                        reg = <0 0x11f40000 0 0x1000>;