*/
#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
+#include <asm/system.h>
#include <errno.h>
#include <fuse.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <spl.h>
+#include <linux/delay.h>
#define ENET_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
.grp_b7ds = 0x00000030,
};
-static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
- .p0_mpwldectrl0 = 0x0011000E,
- .p0_mpwldectrl1 = 0x000E001B,
- .p1_mpwldectrl0 = 0x00190015,
- .p1_mpwldectrl1 = 0x00070018,
- .p0_mpdgctrl0 = 0x42720306,
- .p0_mpdgctrl1 = 0x026F0266,
- .p1_mpdgctrl0 = 0x4273030A,
- .p1_mpdgctrl1 = 0x02740240,
- .p0_mprddlctl = 0x45393B3E,
- .p1_mprddlctl = 0x403A3747,
- .p0_mpwrdlctl = 0x40434541,
- .p1_mpwrdlctl = 0x473E4A3B,
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = {
+ .p0_mpwldectrl0 = 0x00150019,
+ .p0_mpwldectrl1 = 0x001C000B,
+ .p1_mpwldectrl0 = 0x00020018,
+ .p1_mpwldectrl1 = 0x0002000C,
+ .p0_mpdgctrl0 = 0x43140320,
+ .p0_mpdgctrl1 = 0x03080304,
+ .p1_mpdgctrl0 = 0x43180320,
+ .p1_mpdgctrl1 = 0x03100254,
+ .p0_mprddlctl = 0x4830383C,
+ .p1_mprddlctl = 0x3836323E,
+ .p0_mpwrdlctl = 0x3E444642,
+ .p1_mpwrdlctl = 0x42344442,
};
-static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
+ .p0_mpwldectrl0 = 0x0040003C,
+ .p0_mpwldectrl1 = 0x0032003E,
+ .p0_mpdgctrl0 = 0x42350231,
+ .p0_mpdgctrl1 = 0x021A0218,
+ .p0_mprddlctl = 0x4B4B4E49,
+ .p0_mpwrdlctl = 0x3F3F3035,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
+ .p0_mpwldectrl0 = 0x001a001a,
+ .p0_mpwldectrl1 = 0x00260015,
+ .p0_mpdgctrl0 = 0x030c0320,
+ .p0_mpdgctrl1 = 0x03100304,
+ .p0_mprddlctl = 0x432e3538,
+ .p0_mpwrdlctl = 0x363f423d,
+ .p1_mpwldectrl0 = 0x0006001e,
+ .p1_mpwldectrl1 = 0x00050015,
+ .p1_mpdgctrl0 = 0x031c0324,
+ .p1_mpdgctrl1 = 0x030c0258,
+ .p1_mprddlctl = 0x3834313f,
+ .p1_mpwrdlctl = 0x47374a42,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
+ .p0_mpwldectrl0 = 0x003A003A,
+ .p0_mpwldectrl1 = 0x0030002F,
+ .p1_mpwldectrl0 = 0x002F0038,
+ .p1_mpwldectrl1 = 0x00270039,
+ .p0_mpdgctrl0 = 0x420F020F,
+ .p0_mpdgctrl1 = 0x01760175,
+ .p1_mpdgctrl0 = 0x41640171,
+ .p1_mpdgctrl1 = 0x015E0160,
+ .p0_mprddlctl = 0x45464B4A,
+ .p1_mprddlctl = 0x49484A46,
+ .p0_mpwrdlctl = 0x40402E32,
+ .p1_mpwrdlctl = 0x3A3A3231,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = {
+ .p0_mpwldectrl0 = 0x0040003C,
+ .p0_mpwldectrl1 = 0x0032003E,
+ .p0_mpdgctrl0 = 0x42350231,
+ .p0_mpdgctrl1 = 0x021A0218,
+ .p0_mprddlctl = 0x4B4B4E49,
+ .p0_mpwrdlctl = 0x3F3F3035,
+};
+
+/*
+ * 2 Gbit DDR3 memory
+ * - NANYA #NT5CC128M16IP-DII
+ * - NANYA #NT5CB128M16FP-DII
+ */
+static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = {
.mem_speed = 1600,
.density = 2,
- .width = 64,
+ .width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
- .trcd = 1312,
+ .trcd = 1375,
.trcmin = 5863,
.trasmin = 3750,
};
-static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
+/*
+ * 4 Gbit DDR3 memory
+ * - Intelligent Memory #IM4G16D3EABG-125I
+ */
+static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* DDR3 64bit */
+static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
- .cs_density = 16,
+ .cs_density = 32,
+ .ncs = 1, /* single chip select */
+ .cs1_mirror = 1,
+ .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+ .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .refsel = 1, /* Refresh cycles at 32KHz */
+ .refr = 3, /* 4 refresh commands per refresh cycle */
+};
+
+/* DDR3 32bit */
+static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = {
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = 1,
+ .cs_density = 32,
.ncs = 1, /* single chip select */
.cs1_mirror = 1,
.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
/* SPI */
static iomux_v3_cfg_t const ecspi1_pads[] = {
- /* SS0 */
- IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ /* SS0 - SS of boot flash */
+ IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 |
+ MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+ /* SS2 - SS of DHCOM SPI1 */
+ IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 |
+ MUX_PAD_CTRL(SPI_PAD_CTRL | PAD_CTL_PUS_100K_UP)),
+
IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
SETUP_IOMUX_PADS(uart1_pads);
}
+#ifdef CONFIG_FSL_USDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 1;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* eMMC/uSDHC4 is always present */
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ SETUP_IOMUX_PADS(usdhc4_pads);
+ usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
/* USB */
static iomux_v3_cfg_t const usb_pads[] = {
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
SETUP_IOMUX_PADS(usb_pads);
}
+/* Perform DDR DRAM calibration */
+static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+ int ret = 0;
+
+#ifdef CONFIG_MX6_DDRCAL
+ udelay(100);
+ ret = mmdc_do_write_level_calibration(sysinfo);
+ if (ret) {
+ printf("DDR3: Write level calibration error [%d]\n", ret);
+ return ret;
+ }
+
+ ret = mmdc_do_dqs_calibration(sysinfo);
+ if (ret) {
+ printf("DDR3: DQS calibration error [%d]\n", ret);
+ return ret;
+ }
+#endif /* CONFIG_MX6_DDRCAL */
+
+ return ret;
+}
+
+
+/* DRAM */
+static void dhcom_spl_dram_init(void)
+{
+ enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code();
+
+ if (is_mx6dq()) {
+ mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs,
+ &dhcom6dq_grp_ioregs);
+ switch (ddr3_code) {
+ default:
+ printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code);
+ printf(" choosing 1024 MB\n");
+ /* fall through */
+ case DH_DDR3_SIZE_1GIB:
+ mx6_dram_cfg(&dhcom_ddr_64bit,
+ &dhcom_mmdc_calib_4x2g_1066,
+ &dhcom_mem_ddr_2g);
+ break;
+ case DH_DDR3_SIZE_2GIB:
+ mx6_dram_cfg(&dhcom_ddr_64bit,
+ &dhcom_mmdc_calib_4x4g_1066,
+ &dhcom_mem_ddr_4g);
+ break;
+ }
+
+ /* Perform DDR DRAM calibration */
+ spl_dram_perform_cal(&dhcom_ddr_64bit);
+
+ } else if (is_cpu_type(MXC_CPU_MX6DL)) {
+ mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
+ &dhcom6sdl_grp_ioregs);
+ switch (ddr3_code) {
+ default:
+ printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code);
+ printf(" choosing 1024 MB\n");
+ /* fall through */
+ case DH_DDR3_SIZE_1GIB:
+ mx6_dram_cfg(&dhcom_ddr_64bit,
+ &dhcom_mmdc_calib_4x2g_800,
+ &dhcom_mem_ddr_2g);
+ break;
+ }
+
+ /* Perform DDR DRAM calibration */
+ spl_dram_perform_cal(&dhcom_ddr_64bit);
+
+ } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+ mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
+ &dhcom6sdl_grp_ioregs);
+ switch (ddr3_code) {
+ default:
+ printf("imx6s: unsupported ddr3 code %d\n", ddr3_code);
+ printf(" choosing 512 MB\n");
+ /* fall through */
+ case DH_DDR3_SIZE_512MIB:
+ mx6_dram_cfg(&dhcom_ddr_32bit,
+ &dhcom_mmdc_calib_2x2g_800,
+ &dhcom_mem_ddr_2g);
+ break;
+ case DH_DDR3_SIZE_1GIB:
+ mx6_dram_cfg(&dhcom_ddr_32bit,
+ &dhcom_mmdc_calib_2x4g_800,
+ &dhcom_mem_ddr_4g);
+ break;
+ }
+
+ /* Perform DDR DRAM calibration */
+ spl_dram_perform_cal(&dhcom_ddr_32bit);
+ }
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+ int i;
+
+ set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
+ set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
+
+ for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT;
+ i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) +
+ (SZ_1G >> MMU_SECTION_SHIFT));
+ i++)
+ set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
+
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
- /* Start the DDR DRAM */
- if (is_mx6dq())
- mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
- &dhcom6dq_grp_ioregs);
- else
- mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
- &dhcom6sdl_grp_ioregs);
- mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
+ /* DDR3 initialization */
+ dhcom_spl_dram_init();
- /* Perform DDR DRAM calibration */
- udelay(100);
- mmdc_do_dqs_calibration(&dhcom_ddr_info);
+ /* Set up early MMU tables at the beginning of DRAM and start d-cache */
+ gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M;
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ enable_caches();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
+
+void spl_board_prepare_for_boot(void)
+{
+ /*
+ * Flush and disable dcache. Without it, the following bootstage might fail randomly because
+ * dirty cache lines may not have been written back to DRAM.
+ *
+ * If dcache_disable() would be omitted, the following scenario may occur:
+ *
+ * The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled
+ * in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations
+ * have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old
+ * state of the content.
+ *
+ * Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was
+ * disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data.
+ */
+ dcache_disable(); /* implies flush_dcache_all() */
+}
projects / u-boot.git / blobdiff