#include <common.h>
#include <dm.h>
#include <mmc.h>
+#include <reset-uclass.h>
#include <sdhci.h>
#include <asm/arch/sdhci.h>
struct sti_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
+ struct reset_ctl reset;
+ int instance;
};
-/*
- * used to get access to MMC1 reset,
- * will be removed when STi reset driver will be available
- */
-#define STIH410_SYSCONF5_BASE 0x092b0000
-
/**
* sti_mmc_core_config: configure the Arasan HC
- * @regbase: base address
- * @mmc_instance: mmc instance id
+ * @dev : udevice
+ *
* Description: this function is to configure the Arasan MMC HC.
* This should be called when the system starts in case of, on the SoC,
* it is needed to configure the host controller.
* W/o these settings the SDHCI could configure and use the embedded controller
* with limited features.
*/
-static void sti_mmc_core_config(const u32 regbase, int mmc_instance)
+static int sti_mmc_core_config(struct udevice *dev)
{
- unsigned long *sysconf;
+ struct sti_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
/* only MMC1 has a reset line */
- if (mmc_instance) {
- sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE +
- ST_MMC_CCONFIG_REG_5);
- generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf);
+ if (plat->instance) {
+ ret = reset_deassert(&plat->reset);
+ if (ret < 0) {
+ pr_err("MMC1 deassert failed: %d", ret);
+ return ret;
+ }
}
writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
- regbase + FLASHSS_MMC_CORE_CONFIG_1);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_1);
- if (mmc_instance) {
+ if (plat->instance) {
writel(STI_FLASHSS_MMC_CORE_CONFIG2,
- regbase + FLASHSS_MMC_CORE_CONFIG_2);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
writel(STI_FLASHSS_MMC_CORE_CONFIG3,
- regbase + FLASHSS_MMC_CORE_CONFIG_3);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
} else {
writel(STI_FLASHSS_SDCARD_CORE_CONFIG2,
- regbase + FLASHSS_MMC_CORE_CONFIG_2);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
writel(STI_FLASHSS_SDCARD_CORE_CONFIG3,
- regbase + FLASHSS_MMC_CORE_CONFIG_3);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
}
writel(STI_FLASHSS_MMC_CORE_CONFIG4,
- regbase + FLASHSS_MMC_CORE_CONFIG_4);
+ host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4);
+
+ return 0;
}
static int sti_sdhci_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sti_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
- int ret, mmc_instance;
+ int ret;
/*
* identify current mmc instance, mmc1 has a reset, not mmc0
* MMC0 is wired to the SD slot,
* MMC1 is wired on the high speed connector
*/
-
- if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL))
- mmc_instance = 1;
+ ret = reset_get_by_index(dev, 0, &plat->reset);
+ if (!ret)
+ plat->instance = 1;
else
- mmc_instance = 0;
+ if (ret == -ENOENT)
+ plat->instance = 0;
+ else
+ return ret;
- sti_mmc_core_config((const u32) host->ioaddr, mmc_instance);
+ ret = sti_mmc_core_config(dev);
+ if (ret)
+ return ret;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_32BIT_DMA_ADDR |