+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
+#include <init.h>
+#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
-#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
-#include <usb.h>
-#include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_SRE_FAST)
-#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+#define ETH_PHY_POWER IMX_GPIO_NR(4, 21)
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = imx_ddr_size();
return 0;
}
MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+#ifdef CONFIG_SPL_BUILD
static iomux_v3_cfg_t const usdhc1_pads[] = {
/* 8 bit SD */
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/*CD pin*/
MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+#endif
-static iomux_v3_cfg_t const fec_pads[] = {
- MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
-#ifdef CONFIG_MXC_SPI
-static iomux_v3_cfg_t ecspi1_pads[] = {
- MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
{
- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+ struct udevice *dev;
+ int ret;
+ u32 dev_id, rev_id, i;
+ u32 switch_num = 6;
+ u32 offset = PFUZE100_SW1CMODE;
+
+ ret = pmic_get("pfuze100@08", &dev);
+ if (ret == -ENODEV)
+ return 0;
+
+ if (ret != 0)
+ return ret;
+
+ dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+ /* set SW1AB staby volatage 0.975V */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+ /* set SW1C staby volatage 0.975V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
+ /* Init mode to APS_PFM */
+ pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+ for (i = 0; i < switch_num - 1; i++)
+ pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+ return 0;
}
+#endif
-static void setup_spi(void)
+#ifdef CONFIG_FEC_MXC
+
+static int setup_fec(void)
{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* clear gpr1[14], gpr1[18:17] to select anatop clock */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
+
+ return enable_fec_anatop_clock(0, ENET_50MHZ);
}
#endif
-static void setup_iomux_uart(void)
+int board_early_init_f(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ setup_iomux_uart();
+
+ return 0;
}
-static void setup_iomux_fec(void)
+int board_init(void)
{
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- /* Reset LAN8720 PHY */
- gpio_direction_output(ETH_PHY_RESET , 0);
- udelay(25000);
- gpio_set_value(ETH_PHY_RESET, 1);
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+ return 0;
}
+int checkboard(void)
+{
+ puts("Board: MX6SLEVK\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <linux/libfdt.h>
+
#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
+ gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC2_BASE_ADDR:
+ gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
+ gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
}
return ret;
}
-int board_mmc_init(bd_t *bis)
+int board_mmc_init(struct bd_info *bis)
{
-#ifndef CONFIG_SPL_BUILD
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
- * mmc0 USDHC1
- * mmc1 USDHC2
- * mmc2 USDHC3
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- gpio_direction_input(USDHC3_CD_GPIO);
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize "
- "mmc dev %d\n", i);
- return ret;
- }
- }
-
- return 0;
-#else
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
}
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-struct i2c_pads_info i2c_pad_info1 = {
- .sda = {
- .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
- .gp = IMX_GPIO_NR(3, 13),
- },
- .scl = {
- .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
- .gp = IMX_GPIO_NR(3, 12),
- },
-};
-
-int power_init_board(void)
-{
- struct pmic *p;
-
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
- return -ENODEV;
-
- return pfuze_mode_init(p, APS_PFM);
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_fec();
-
- return cpu_eth_init(bis);
-}
-
-static int setup_fec(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- /* clear gpr1[14], gpr1[18:17] to select anatop clock */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
-
- return enable_fec_anatop_clock(0, ENET_50MHZ);
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET 0x800
-#define UCTRL_PWR_POL (1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
- /* OTG1 */
- MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
- /* OTG2 */
- MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-static void setup_usb(void)
-{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return usb_phy_mode(port);
-}
-
-int board_ehci_hcd_init(int port)
-{
- u32 *usbnc_usb_ctrl;
-
- if (port > 1)
- return -EINVAL;
-
- usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
- port * 4);
-
- /* Set Power polarity */
- setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
- return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
-#ifdef CONFIG_MXC_SPI
- setup_spi();
-#endif
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-#endif
-
-#ifdef CONFIG_FEC_MXC
- setup_fec();
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: MX6SLEVK\n");
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#include <libfdt.h>
-
const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_sdqs0 = 0x00003030,
.dram_sdqs1 = 0x00003030,
.sde_to_rst = 0, /* LPDDR2 does not need this field */
.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
.ddr_type = DDR_TYPE_LPDDR2,
+ .refsel = 0, /* Refresh cycles at 64KHz */
+ .refr = 3, /* 4 refresh commands per refresh cycle */
};
mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);