+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <malloc.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <dwmmc.h>
-#include <errno.h>
-#include <asm/arch/dwmmc.h>
+#include <log.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/system_manager.h>
+#include <clk.h>
+#include <dm.h>
+#include <dwmmc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <dm/device_compat.h>
+#include <linux/libfdt.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <reset.h>
-static const struct socfpga_clock_manager *clock_manager_base =
- (void *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
- (void *)SOCFPGA_SYSMGR_ADDRESS;
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_dwmci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
-/* socfpga implmentation specific drver private data */
+/* socfpga implmentation specific driver private data */
struct dwmci_socfpga_priv_data {
- unsigned int drvsel;
- unsigned int smplsel;
+ struct dwmci_host host;
+ unsigned int drvsel;
+ unsigned int smplsel;
};
+static void socfpga_dwmci_reset(struct udevice *dev)
+{
+ struct reset_ctl_bulk reset_bulk;
+ int ret;
+
+ ret = reset_get_bulk(dev, &reset_bulk);
+ if (ret) {
+ dev_warn(dev, "Can't get reset: %d\n", ret);
+ return;
+ }
+
+ reset_deassert_bulk(&reset_bulk);
+}
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
+ u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
+ ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
/* Disable SDMMC clock. */
- clrbits_le32(&clock_manager_base->per_pll.en,
- CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+ clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+ CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
- writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
- &system_manager_base->sdmmcgrp_ctrl);
+ writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
- readl(&system_manager_base->sdmmcgrp_ctrl));
+ readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
/* Enable SDMMC clock */
- setbits_le32(&clock_manager_base->per_pll.en,
- CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+ CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
}
-static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
+static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
{
- /* FIXME: probe from DT eventually too/ */
- const unsigned long clk = cm_get_mmc_controller_clk_hz();
+ struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+ int ret;
- struct dwmci_host *host;
- struct dwmci_socfpga_priv_data *priv;
- fdt_addr_t reg_base;
- int bus_width, fifo_depth;
+ ret = clk_get_by_index(dev, 1, &clk);
+ if (ret)
+ return ret;
- if (clk == 0) {
- printf("DWMMC%d: MMC clock is zero!", idx);
- return -EINVAL;
- }
+ host->bus_hz = clk_get_rate(&clk);
- /* Get the register address from the device node */
- reg_base = fdtdec_get_addr(blob, node, "reg");
- if (!reg_base) {
- printf("DWMMC%d: Can't get base address\n", idx);
+ clk_free(&clk);
+#else
+ /* Fixed clock divide by 4 which due to the SDMMC wrapper */
+ host->bus_hz = cm_get_mmc_controller_clk_hz();
+#endif
+ if (host->bus_hz == 0) {
+ printf("DWMMC: MMC clock is zero!");
return -EINVAL;
}
- /* Get the bus width from the device node */
- bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
- if (bus_width <= 0) {
- printf("DWMMC%d: Can't get bus-width\n", idx);
- return -EINVAL;
- }
+ return 0;
+}
+
+static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ int fifo_depth;
- fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
+ fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-depth", 0);
if (fifo_depth < 0) {
- printf("DWMMC%d: Can't get FIFO depth\n", idx);
+ printf("DWMMC: Can't get FIFO depth\n");
return -EINVAL;
}
- /* Allocate the host */
- host = calloc(1, sizeof(*host));
- if (!host)
- return -ENOMEM;
-
- /* Allocate the priv */
- priv = calloc(1, sizeof(*priv));
- if (!priv) {
- free(host);
- return -ENOMEM;
- }
-
- host->name = "SOCFPGA DWMMC";
- host->ioaddr = (void *)reg_base;
- host->buswidth = bus_width;
+ host->name = dev->name;
+ host->ioaddr = (void *)devfdt_get_addr(dev);
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 4);
host->clksel = socfpga_dwmci_clksel;
- host->dev_index = idx;
- /* Fixed clock divide by 4 which due to the SDMMC wrapper */
- host->bus_hz = clk;
+
+ /*
+ * We only have one dwmmc block on gen5 SoCFPGA.
+ */
+ host->dev_index = 0;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
- priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
- priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
+ priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
+ "drvsel", 3);
+ priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
+ "smplsel", 0);
host->priv = priv;
- return add_dwmci(host, host->bus_hz, 400000);
+ return 0;
}
-static int socfpga_dwmci_process_node(const void *blob, int nodes[],
- int count)
+static int socfpga_dwmmc_probe(struct udevice *dev)
{
- int i, node, ret;
-
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = socfpga_dwmci_of_probe(blob, node, i);
- if (ret) {
- printf("%s: failed to decode dev %d\n", __func__, i);
- return ret;
- }
- }
- return 0;
+#ifdef CONFIG_BLK
+ struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
+#endif
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ int ret;
+
+ ret = socfpga_dwmmc_get_clk_rate(dev);
+ if (ret)
+ return ret;
+
+ socfpga_dwmci_reset(dev);
+
+#ifdef CONFIG_BLK
+ dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
+ host->mmc = &plat->mmc;
+#else
+
+ ret = add_dwmci(host, host->bus_hz, 400000);
+ if (ret)
+ return ret;
+#endif
+ host->mmc->priv = &priv->host;
+ upriv->mmc = host->mmc;
+ host->mmc->dev = dev;
+
+ return dwmci_probe(dev);
}
-int socfpga_dwmmc_init(const void *blob)
+static int socfpga_dwmmc_bind(struct udevice *dev)
{
- int nodes[2]; /* Max. two controllers. */
- int ret, count;
+#ifdef CONFIG_BLK
+ struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
+ int ret;
- count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_ALTERA_SOCFPGA_DWMMC,
- nodes, ARRAY_SIZE(nodes));
+ ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+ if (ret)
+ return ret;
+#endif
- ret = socfpga_dwmci_process_node(blob, nodes, count);
-
- return ret;
+ return 0;
}
+
+static const struct udevice_id socfpga_dwmmc_ids[] = {
+ { .compatible = "altr,socfpga-dw-mshc" },
+ { }
+};
+
+U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
+ .name = "socfpga_dwmmc",
+ .id = UCLASS_MMC,
+ .of_match = socfpga_dwmmc_ids,
+ .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
+ .ops = &dm_dwmci_ops,
+ .bind = socfpga_dwmmc_bind,
+ .probe = socfpga_dwmmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
+ .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
+};
projects / u-boot.git / blobdiff