Convert CONFIG_I2C_SET_DEFAULT_BUS_NUM et al to Kconfig

[u-boot.git] / include / configs / P1010RDB.h

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 1152bca03be6491b3e4deb94cedfaef9bb14d16e..b3fadc6da2c3df168c18f2c5cd65f5cae3b9e371 100644 (file)
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -10,6 +11,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <linux/stringify.h>
+
 #include <asm/config_mpc85xx.h>
 #define CONFIG_NAND_FSL_IFC
 
@@ -29,7 +32,7 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_RESET_VECTOR_ADDRESS    0x110bfffc
 #else
@@ -49,8 +52,8 @@
 #endif
 #endif
 
-#ifdef CONFIG_NAND
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_MTD_RAW_NAND
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
@@ -113,8 +116,6 @@
 #if defined(CONFIG_PCI)
 #define CONFIG_PCIE1                   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2                   /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 /*
@@ -122,19 +123,13 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME          "mini PCIe Slot"
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
 #endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xfffc00000ull
 #else
@@ -142,23 +137,13 @@
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_PCIE2_NAME          "PCIe Slot"
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_PCIE2_NAME          "mini PCIe Slot"
-#endif
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
 #endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xfffc10000ull
 #else
@@ -168,8 +153,6 @@
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
 #endif
 
-#define CONFIG_ENV_OVERWRITE
-
 #define CONFIG_DDR_CLK_FREQ    66666666 /* DDRCLK on P1010 RDB */
 #define CONFIG_SYS_CLK_FREQ    66666666 /* SYSCLK for P1010 RDB */
 
@@ -183,14 +166,6 @@
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP                        1
-#define CONFIG_SYS_NUM_ADDR_MAP                16      /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END         0x1fffffff
-
 /* DDR Setup */
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
@@ -388,7 +363,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NAND_DDR_LAW                11
 
 /* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
@@ -484,7 +459,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (128 << 10)
 #define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_INIT_L2_ADDR                0xD0000000
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
@@ -522,33 +497,19 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 
 /* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED       400000
-#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED      400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
 #define I2C_PCA9557_ADDR1              0x18
 #define I2C_PCA9557_ADDR2              0x19
 #define I2C_PCA9557_BUS_NUM            0
 
 /* I2C EEPROM */
 #if defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_ID_EEPROM
 #ifdef CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 #define MAX_NUM_PORTS                  9 /* for 128Bytes EEPROM */
 #endif
 /* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
 /* RTC */
 #define CONFIG_RTC_PT7C4338
@@ -558,7 +519,7 @@ extern unsigned long get_sdram_size(void);
  * SPI interface will not be available in case of NAND boot SPI CS0 will be
  * used for SLIC
  */
-#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
+#if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
 /* eSPI - Enhanced SPI */
 #endif
 
@@ -628,33 +589,16 @@ extern unsigned long get_sdram_size(void);
  */
 #if defined(CONFIG_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_SYS_MMC_ENV_DEV         0
-#define CONFIG_ENV_SIZE                        0x2000
-#elif defined(CONFIG_SPIFLASH)
-#define CONFIG_ENV_OFFSET      0x100000        /* 1MB */
-#define CONFIG_ENV_SECT_SIZE   0x10000
-#define CONFIG_ENV_SIZE                0x2000
-#elif defined(CONFIG_NAND)
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR           (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #else
 #if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_ENV_SIZE                CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_RANGE       (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_ENV_SIZE                (16 * 1024)
 #define CONFIG_ENV_RANGE       (32 * CONFIG_ENV_SIZE) /* new block size 512K */
 #endif
 #endif
-#define CONFIG_ENV_OFFSET      (1024 * 1024)
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_ADDR                        (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE                        0x2000
-#else
-#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
 #endif
 
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */