+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Common configuration header file for all Keystone II EVM platforms
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_KS2_EVM_H
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF
CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
KEYSTONE_SPL_STACK_SIZE - 4)
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* SRAM scratch space entries */
#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
-#define CONFIG_CONS_INDEX 1
#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
#endif
/* Network Configuration */
-#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 32
#define CONFIG_ENV_EEPROM_IS_ON_I2C
/* NAND Configuration */
-#define CONFIG_NAND_DAVINCI
#define CONFIG_KEYSTONE_RBL_NAND
#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
#define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-#define CONFIG_MTD_PARTITIONS
/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE