Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into dts/upstream

[u-boot.git] / dts / upstream / src / arm / st / stm32mp153.dtsi

diff --git a/dts/upstream/src/arm/st/stm32mp153.dtsi b/dts/upstream/src/arm/st/stm32mp153.dtsi
index 486084e0b80b5df0fc3c581641918c90c23dbe2a..4640dafb1598c2701b6db1903530636a78e60369 100644 (file)
--- a/dts/upstream/src/arm/st/stm32mp153.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp153.dtsi
@@ -28,32 +28,34 @@
                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
        };
+};
 
-       soc {
-               m_can1: can@4400e000 {
-                       compatible = "bosch,m_can";
-                       reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
-                       reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "int0", "int1";
-                       clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-                       clock-names = "hclk", "cclk";
-                       bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
-                       status = "disabled";
-               };
+&etzpc {
+       m_can1: can@4400e000 {
+               compatible = "bosch,m_can";
+               reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+               reg-names = "m_can", "message_ram";
+               interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+               clock-names = "hclk", "cclk";
+               bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+               access-controllers = <&etzpc 62>;
+               status = "disabled";
+       };
 
-               m_can2: can@4400f000 {
-                       compatible = "bosch,m_can";
-                       reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
-                       reg-names = "m_can", "message_ram";
-                       interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "int0", "int1";
-                       clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-                       clock-names = "hclk", "cclk";
-                       bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
-                       status = "disabled";
-               };
+       m_can2: can@4400f000 {
+               compatible = "bosch,m_can";
+               reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+               reg-names = "m_can", "message_ram";
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "int0", "int1";
+               clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+               clock-names = "hclk", "cclk";
+               bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+               access-controllers = <&etzpc 62>;
+               status = "disabled";
        };
 };