tools: kwboot: Fix parsing UART image without data checksum

[u-boot.git] / drivers / ddr / fsl / arm_ddr_gen3.c

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 7160da4ec89722b5c9f6023e6908eac4e1fd2002..9dada5e11756fb45b5c383bb7efaf1a1cd382a72 100644 (file)
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -1,17 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  * Derived from mpc85xx_ddr_gen3.c, removed all workarounds
  */
 
 #include <common.h>
+#include <log.h>
 #include <asm/io.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/processor.h>
 #include <fsl_immap.h>
 #include <fsl_ddr.h>
+#include <asm/arch/clock.h>
+#include <linux/delay.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -38,19 +40,19 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
        switch (ctrl_num) {
        case 0:
-               ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
                break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
        case 1:
-               ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
        case 2:
-               ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+               ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
        case 3:
                ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
                break;
@@ -128,7 +130,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        if (is_warm_boot()) {
                ddr_out32(&ddr->sdram_cfg_2,
                          regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
-               ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+               ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
                ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 
                /* DRAM VRef will not be trained */