include/phy_interface.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  *      Andy Fleming <afleming@gmail.com>
   6  *
   7  * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
   8  */
   9
  10 #ifndef _PHY_INTERFACE_H
  11 #define _PHY_INTERFACE_H
  12
  13 #include <string.h>
  14 #include <linux/kernel.h>
  15
  16 typedef enum {
  17         PHY_INTERFACE_MODE_NA, /* don't touch */
  18         PHY_INTERFACE_MODE_INTERNAL,
  19         PHY_INTERFACE_MODE_MII,
  20         PHY_INTERFACE_MODE_GMII,
  21         PHY_INTERFACE_MODE_SGMII,
  22         PHY_INTERFACE_MODE_TBI,
  23         PHY_INTERFACE_MODE_REVMII,
  24         PHY_INTERFACE_MODE_RMII,
  25         PHY_INTERFACE_MODE_REVRMII,
  26         PHY_INTERFACE_MODE_RGMII,
  27         PHY_INTERFACE_MODE_RGMII_ID,
  28         PHY_INTERFACE_MODE_RGMII_RXID,
  29         PHY_INTERFACE_MODE_RGMII_TXID,
  30         PHY_INTERFACE_MODE_RTBI,
  31         PHY_INTERFACE_MODE_SMII,
  32         PHY_INTERFACE_MODE_XGMII,
  33         PHY_INTERFACE_MODE_XLGMII,
  34         PHY_INTERFACE_MODE_MOCA,
  35         PHY_INTERFACE_MODE_QSGMII,
  36         PHY_INTERFACE_MODE_TRGMII,
  37         PHY_INTERFACE_MODE_100BASEX,
  38         PHY_INTERFACE_MODE_1000BASEX,
  39         PHY_INTERFACE_MODE_2500BASEX,
  40         PHY_INTERFACE_MODE_5GBASER,
  41         PHY_INTERFACE_MODE_RXAUI,
  42         PHY_INTERFACE_MODE_XAUI,
  43         /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
  44         PHY_INTERFACE_MODE_10GBASER,
  45         PHY_INTERFACE_MODE_25GBASER,
  46         PHY_INTERFACE_MODE_USXGMII,
  47         /* 10GBASE-KR - with Clause 73 AN */
  48         PHY_INTERFACE_MODE_10GKR,
  49         PHY_INTERFACE_MODE_QUSGMII,
  50         PHY_INTERFACE_MODE_1000BASEKX,
  51 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
  52         /* LX2160A SERDES modes */
  53         PHY_INTERFACE_MODE_25G_AUI,
  54         PHY_INTERFACE_MODE_XLAUI,
  55         PHY_INTERFACE_MODE_CAUI2,
  56         PHY_INTERFACE_MODE_CAUI4,
  57 #endif
  58 #if defined(CONFIG_PHY_NCSI)
  59         PHY_INTERFACE_MODE_NCSI,
  60 #endif
  61         PHY_INTERFACE_MODE_MAX,
  62 } phy_interface_t;
  63
  64 static const char * const phy_interface_strings[] = {
  65         [PHY_INTERFACE_MODE_NA]                 = "",
  66         [PHY_INTERFACE_MODE_INTERNAL]           = "internal",
  67         [PHY_INTERFACE_MODE_MII]                = "mii",
  68         [PHY_INTERFACE_MODE_GMII]               = "gmii",
  69         [PHY_INTERFACE_MODE_SGMII]              = "sgmii",
  70         [PHY_INTERFACE_MODE_TBI]                = "tbi",
  71         [PHY_INTERFACE_MODE_REVMII]             = "rev-mii",
  72         [PHY_INTERFACE_MODE_RMII]               = "rmii",
  73         [PHY_INTERFACE_MODE_REVRMII]            = "rev-rmii",
  74         [PHY_INTERFACE_MODE_RGMII]              = "rgmii",
  75         [PHY_INTERFACE_MODE_RGMII_ID]           = "rgmii-id",
  76         [PHY_INTERFACE_MODE_RGMII_RXID]         = "rgmii-rxid",
  77         [PHY_INTERFACE_MODE_RGMII_TXID]         = "rgmii-txid",
  78         [PHY_INTERFACE_MODE_RTBI]               = "rtbi",
  79         [PHY_INTERFACE_MODE_SMII]               = "smii",
  80         [PHY_INTERFACE_MODE_XGMII]              = "xgmii",
  81         [PHY_INTERFACE_MODE_XLGMII]             = "xlgmii",
  82         [PHY_INTERFACE_MODE_MOCA]               = "moca",
  83         [PHY_INTERFACE_MODE_QSGMII]             = "qsgmii",
  84         [PHY_INTERFACE_MODE_TRGMII]             = "trgmii",
  85         [PHY_INTERFACE_MODE_1000BASEX]          = "1000base-x",
  86         [PHY_INTERFACE_MODE_1000BASEKX]         = "1000base-kx",
  87         [PHY_INTERFACE_MODE_2500BASEX]          = "2500base-x",
  88         [PHY_INTERFACE_MODE_5GBASER]            = "5gbase-r",
  89         [PHY_INTERFACE_MODE_RXAUI]              = "rxaui",
  90         [PHY_INTERFACE_MODE_XAUI]               = "xaui",
  91         [PHY_INTERFACE_MODE_10GBASER]           = "10gbase-r",
  92         [PHY_INTERFACE_MODE_25GBASER]           = "25gbase-r",
  93         [PHY_INTERFACE_MODE_USXGMII]            = "usxgmii",
  94         [PHY_INTERFACE_MODE_10GKR]              = "10gbase-kr",
  95         [PHY_INTERFACE_MODE_100BASEX]           = "100base-x",
  96         [PHY_INTERFACE_MODE_QUSGMII]            = "qusgmii",
  97 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
  98         /* LX2160A SERDES modes */
  99         [PHY_INTERFACE_MODE_25G_AUI]            = "25g-aui",
 100         [PHY_INTERFACE_MODE_XLAUI]              = "xlaui4",
 101         [PHY_INTERFACE_MODE_CAUI2]              = "caui2",
 102         [PHY_INTERFACE_MODE_CAUI4]              = "caui4",
 103 #endif
 104 #if defined(CONFIG_PHY_NCSI)
 105         [PHY_INTERFACE_MODE_NCSI]               = "NC-SI",
 106 #endif
 107 };
 108
 109 /* Backplane modes:
 110  * are considered a sub-type of phy_interface_t: XGMII
 111  * and are specified in "phy-connection-type" with one of the following strings
 112  */
 113 static const char * const backplane_mode_strings[] = {
 114         "10gbase-kr",
 115         "40gbase-kr4",
 116 };
 117
 118 static inline const char *phy_string_for_interface(phy_interface_t i)
 119 {
 120         /* Default to unknown */
 121         if (i >= PHY_INTERFACE_MODE_MAX)
 122                 i = PHY_INTERFACE_MODE_NA;
 123
 124         return phy_interface_strings[i];
 125 }
 126
 127 static inline bool is_backplane_mode(const char *phyconn)
 128 {
 129         int i;
 130
 131         if (!phyconn)
 132                 return false;
 133         for (i = 0; i < ARRAY_SIZE(backplane_mode_strings); i++) {
 134                 if (!strcmp(phyconn, backplane_mode_strings[i]))
 135                         return true;
 136         }
 137         return false;
 138 }
 139
 140 #endif /* _PHY_INTERFACE_H */