1 // SPDX-License-Identifier: GPL-2.0
3 * Allwinner SUNXI "glue layer"
5 * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
6 * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
8 * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
9 * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
10 * javen <javen@allwinnertech.com>
12 * Based on the DA8xx "glue layer" code.
13 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C) 2005-2006 by Texas Instruments
16 * This file is part of the Inventra Controller Driver for Linux.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/usb_phy.h>
24 #include <asm-generic/gpio.h>
27 #include <linux/usb/musb.h>
28 #include "linux-compat.h"
29 #include "musb_core.h"
30 #include "musb_uboot.h"
32 /******************************************************************************
33 ******************************************************************************
34 * From the Allwinner driver
35 ******************************************************************************
36 ******************************************************************************/
38 /******************************************************************************
39 * From include/sunxi_usb_bsp.h
40 ******************************************************************************/
43 #define USBC_REG_o_ISCR 0x0400
44 #define USBC_REG_o_PHYCTL 0x0404
45 #define USBC_REG_o_PHYBIST 0x0408
46 #define USBC_REG_o_PHYTUNE 0x040c
48 #define USBC_REG_o_VEND0 0x0043
50 /* Interface Status and Control */
51 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
52 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
53 #define USBC_BP_ISCR_EXT_ID_STATUS 28
54 #define USBC_BP_ISCR_EXT_DM_STATUS 27
55 #define USBC_BP_ISCR_EXT_DP_STATUS 26
56 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
57 #define USBC_BP_ISCR_MERGED_ID_STATUS 24
59 #define USBC_BP_ISCR_ID_PULLUP_EN 17
60 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16
61 #define USBC_BP_ISCR_FORCE_ID 14
62 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12
63 #define USBC_BP_ISCR_VBUS_VALID_SRC 10
65 #define USBC_BP_ISCR_HOSC_EN 7
66 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
67 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5
68 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
69 #define USBC_BP_ISCR_IRQ_ENABLE 3
70 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
71 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
72 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
74 /******************************************************************************
76 ******************************************************************************/
78 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
82 temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
83 temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
84 temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
89 static void USBC_EnableIdPullUp(__iomem void *base)
93 reg_val = musb_readl(base, USBC_REG_o_ISCR);
94 reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
95 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
96 musb_writel(base, USBC_REG_o_ISCR, reg_val);
99 static void USBC_EnableDpDmPullUp(__iomem void *base)
103 reg_val = musb_readl(base, USBC_REG_o_ISCR);
104 reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
105 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
106 musb_writel(base, USBC_REG_o_ISCR, reg_val);
109 static void USBC_ForceIdToLow(__iomem void *base)
113 reg_val = musb_readl(base, USBC_REG_o_ISCR);
114 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
115 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
116 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
117 musb_writel(base, USBC_REG_o_ISCR, reg_val);
120 static void USBC_ForceIdToHigh(__iomem void *base)
124 reg_val = musb_readl(base, USBC_REG_o_ISCR);
125 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
126 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
127 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
128 musb_writel(base, USBC_REG_o_ISCR, reg_val);
131 static void USBC_ForceVbusValidToLow(__iomem void *base)
135 reg_val = musb_readl(base, USBC_REG_o_ISCR);
136 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
137 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
138 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
139 musb_writel(base, USBC_REG_o_ISCR, reg_val);
142 static void USBC_ForceVbusValidToHigh(__iomem void *base)
146 reg_val = musb_readl(base, USBC_REG_o_ISCR);
147 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
148 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
149 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
150 musb_writel(base, USBC_REG_o_ISCR, reg_val);
153 static void USBC_ConfigFIFO_Base(void)
157 /* config usb fifo, 8kb mode */
158 reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
159 reg_value &= ~(0x03 << 0);
160 reg_value |= (1 << 0);
161 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
164 /******************************************************************************
165 * Needed for the DFU polling magic
166 ******************************************************************************/
168 static u8 last_int_usb;
170 bool dfu_usb_get_reset(void)
172 return !!(last_int_usb & MUSB_INTR_RESET);
175 /******************************************************************************
177 ******************************************************************************/
179 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
181 struct musb *musb = __hci;
182 irqreturn_t retval = IRQ_NONE;
184 /* read and flush interrupts */
185 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
186 last_int_usb = musb->int_usb;
188 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
189 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
191 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
192 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
194 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
196 if (musb->int_usb || musb->int_tx || musb->int_rx)
197 retval |= musb_interrupt(musb);
202 /* musb_core does not call enable / disable in a balanced manner <sigh> */
203 static bool enabled = false;
205 static int sunxi_musb_enable(struct musb *musb)
209 pr_debug("%s():\n", __func__);
211 musb_ep_select(musb->mregs, 0);
212 musb_writeb(musb->mregs, MUSB_FADDR, 0);
217 /* select PIO mode */
218 musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
220 if (is_host_enabled(musb)) {
221 ret = sunxi_usb_phy_vbus_detect(0);
223 printf("A charger is plugged into the OTG: ");
226 ret = sunxi_usb_phy_id_detect(0);
228 printf("No host cable detected: ");
231 sunxi_usb_phy_power_on(0); /* port power on */
234 USBC_ForceVbusValidToHigh(musb->mregs);
240 static void sunxi_musb_disable(struct musb *musb)
242 pr_debug("%s():\n", __func__);
247 if (is_host_enabled(musb))
248 sunxi_usb_phy_power_off(0); /* port power off */
250 USBC_ForceVbusValidToLow(musb->mregs);
251 mdelay(200); /* Wait for the current session to timeout */
256 static int sunxi_musb_init(struct musb *musb)
258 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
260 pr_debug("%s():\n", __func__);
262 musb->isr = sunxi_musb_interrupt;
264 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
265 #ifdef CONFIG_SUNXI_GEN_SUN6I
266 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
268 sunxi_usb_phy_init(0);
270 USBC_ConfigFIFO_Base();
271 USBC_EnableDpDmPullUp(musb->mregs);
272 USBC_EnableIdPullUp(musb->mregs);
274 if (is_host_enabled(musb)) {
276 USBC_ForceIdToLow(musb->mregs);
278 /* Peripheral mode */
279 USBC_ForceIdToHigh(musb->mregs);
281 USBC_ForceVbusValidToHigh(musb->mregs);
286 static const struct musb_platform_ops sunxi_musb_ops = {
287 .init = sunxi_musb_init,
288 .enable = sunxi_musb_enable,
289 .disable = sunxi_musb_disable,
292 static struct musb_hdrc_config musb_config = {
299 static struct musb_hdrc_platform_data musb_plat = {
300 #if defined(CONFIG_USB_MUSB_HOST)
303 .mode = MUSB_PERIPHERAL,
305 .config = &musb_config,
307 .platform_ops = &sunxi_musb_ops,
310 static int musb_usb_probe(struct udevice *dev)
312 struct musb_host_data *host = dev_get_priv(dev);
313 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
314 void *base = dev_read_addr_ptr(dev);
320 priv->desc_before_addr = true;
322 #ifdef CONFIG_USB_MUSB_HOST
323 host->host = musb_init_controller(&musb_plat, NULL, base);
327 ret = musb_lowlevel_init(host);
329 printf("Allwinner mUSB OTG (Host)\n");
331 ret = musb_register(&musb_plat, NULL, base);
333 printf("Allwinner mUSB OTG (Peripheral)\n");
339 static int musb_usb_remove(struct udevice *dev)
341 struct musb_host_data *host = dev_get_priv(dev);
342 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
344 musb_stop(host->host);
346 sunxi_usb_phy_exit(0);
347 #ifdef CONFIG_SUNXI_GEN_SUN6I
348 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
350 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
358 static const struct udevice_id sunxi_musb_ids[] = {
359 { .compatible = "allwinner,sun4i-a10-musb" },
360 { .compatible = "allwinner,sun6i-a31-musb" },
361 { .compatible = "allwinner,sun8i-a33-musb" },
362 { .compatible = "allwinner,sun8i-h3-musb" },
366 U_BOOT_DRIVER(usb_musb) = {
367 .name = "sunxi-musb",
368 #ifdef CONFIG_USB_MUSB_HOST
371 .id = UCLASS_USB_DEV_GENERIC,
373 .of_match = sunxi_musb_ids,
374 .probe = musb_usb_probe,
375 .remove = musb_usb_remove,
376 #ifdef CONFIG_USB_MUSB_HOST
377 .ops = &musb_usb_ops,
379 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
380 .priv_auto_alloc_size = sizeof(struct musb_host_data),