1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
11 #include <asm/arch-rockchip/boot_mode.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/periph.h>
14 #include <asm/arch-rockchip/misc.h>
15 #include <power/regulator.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 __weak int rk_board_late_init(void)
24 int board_late_init(void)
28 return rk_board_late_init();
35 #ifdef CONFIG_DM_REGULATOR
36 ret = regulators_enable_boot_on(false);
38 debug("%s: Cannot enable boot on regulator\n", __func__);
44 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
45 void enable_caches(void)
47 /* Enable D-cache. I-cache is already enabled in start.S */
52 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
54 #include <usb/dwc2_udc.h>
56 static struct dwc2_plat_otg_data otg_data = {
62 int board_usb_init(int index, enum usb_init_type init)
67 const void *blob = gd->fdt_blob;
69 /* find the usb_otg node */
70 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
73 mode = fdt_getprop(blob, node, "dr_mode", NULL);
74 if (mode && strcmp(mode, "otg") == 0) {
79 node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2");
82 debug("Not found usb_otg device\n");
85 otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
87 return dwc2_udc_probe(&otg_data);
90 int board_usb_cleanup(int index, enum usb_init_type init)
96 #if CONFIG_IS_ENABLED(FASTBOOT)
97 int fastboot_set_reboot_flag(void)
99 printf("Setting reboot to fastboot flag ...\n");
100 /* Set boot mode to fastboot */
101 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
107 #ifdef CONFIG_MISC_INIT_R
108 __weak int misc_init_r(void)
110 const u32 cpuid_offset = 0x7;
111 const u32 cpuid_length = 0x10;
112 u8 cpuid[cpuid_length];
115 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
119 ret = rockchip_cpuid_set(cpuid, cpuid_length);
123 ret = rockchip_setup_macaddr();