1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
10 #include <asm/pl310.h>
11 #include <asm/u-boot.h>
12 #include <asm/utils.h>
14 #include <asm/arch/reset_manager.h>
16 #include <asm/arch/system_manager.h>
17 #include <asm/arch/freeze_controller.h>
18 #include <asm/arch/clock_manager.h>
19 #include <asm/arch/scan_manager.h>
20 #include <asm/arch/sdram.h>
21 #include <asm/arch/scu.h>
22 #include <asm/arch/misc.h>
23 #include <asm/arch/nic301.h>
24 #include <asm/sections.h>
27 #include <asm/arch/pinmux.h>
28 #include <asm/arch/fpga_manager.h>
32 #define FPGA_BUFSIZ 16 * 1024
34 DECLARE_GLOBAL_DATA_PTR;
36 #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
37 #define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
38 SOCFPGA_PHYS_OCRAM_SIZE - \
39 BOOTROM_SHARED_MEM_SIZE)
40 #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
41 static u32 rst_mgr_status __section(.data);
44 * Bootrom will clear the status register in reset manager and stores the
45 * reset status value in shared memory. Bootrom stores shared data at last
47 * This function save reset status provided by BootROM to rst_mgr_status.
48 * More information about reset status register value can be found in reset
49 * manager register description.
50 * When running in debugger without Bootrom, r0 to r3 are random values.
51 * So, skip save the value when r0 is not BootROM shared data address.
53 * r0 - Contains the pointer to the shared memory block. The shared
54 * memory block is located in the top 2 KB of on-chip RAM.
55 * r1 - contains the length of the shared memory.
56 * r2 - unused and set to 0x0.
57 * r3 - points to the version block.
59 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
62 if (r0 == BOOTROM_SHARED_MEM_ADDR)
63 rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
65 save_boot_params_ret();
68 u32 spl_boot_device(void)
70 const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
72 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
73 case 0x1: /* FPGA (HPS2FPGA Bridge) */
74 return BOOT_DEVICE_RAM;
75 case 0x2: /* NAND Flash (1.8V) */
76 case 0x3: /* NAND Flash (3.0V) */
77 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
78 return BOOT_DEVICE_NAND;
79 case 0x4: /* SD/MMC External Transceiver (1.8V) */
80 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
81 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
82 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
83 return BOOT_DEVICE_MMC1;
84 case 0x6: /* QSPI Flash (1.8V) */
85 case 0x7: /* QSPI Flash (3.0V) */
86 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
87 return BOOT_DEVICE_SPI;
89 printf("Invalid boot device (bsel=%08x)!\n", bsel);
94 #ifdef CONFIG_SPL_MMC_SUPPORT
95 u32 spl_boot_mode(const u32 boot_device)
97 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
100 return MMCSD_MODE_RAW;
105 void spl_board_init(void)
107 ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
109 /* enable console uart printing */
110 preloader_console_init();
115 /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
116 if (is_fpgamgr_user_mode()) {
117 int ret = config_pins(gd->fdt_blob, "shared");
122 ret = config_pins(gd->fdt_blob, "fpga");
125 } else if (!is_fpgamgr_early_user_mode()) {
126 /* Program IOSSM(early IO release) or full FPGA */
127 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
130 /* If the IOSSM/full FPGA is already loaded, start DDR */
131 if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
132 ddr_calibration_sequence();
134 if (!is_fpgamgr_user_mode())
135 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
138 void board_init_f(ulong dummy)
140 if (spl_early_init())
143 socfpga_get_managers_addr();
147 socfpga_init_security_policies();
148 socfpga_sdram_remap_zero();
149 socfpga_pl310_clear();
151 /* Assert reset to all except L4WD0 and L4TIMER0 */
152 socfpga_per_reset_all();
153 socfpga_watchdog_disable();
155 /* Configure the clock based on handoff */
156 cm_basic_init(gd->fdt_blob);
158 #ifdef CONFIG_HW_WATCHDOG
159 /* release osc1 watchdog timer 0 from reset */
160 socfpga_reset_deassert_osc1wd0();
162 /* reconfigure and enable the watchdog */
165 #endif /* CONFIG_HW_WATCHDOG */
167 config_dedicated_pins(gd->fdt_blob);