arch/arm/mach-tegra/tegra20/warmboot.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2010 - 2011
   4  * NVIDIA Corporation <www.nvidia.com>
   5  */
   6
   7 #include <asm/global_data.h>
   8 #include <asm/io.h>
   9 #include <linux/errno.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/emc.h>
  12 #include <asm/arch/gp_padctrl.h>
  13 #include <asm/arch/pinmux.h>
  14 #include <asm/arch/sdram_param.h>
  15 #include <asm/arch/tegra.h>
  16 #include <asm/arch-tegra/ap.h>
  17 #include <asm/arch-tegra/apb_misc.h>
  18 #include <asm/arch-tegra/clk_rst.h>
  19 #include <asm/arch-tegra/pmc.h>
  20 #include <asm/arch-tegra/fuse.h>
  21 #include <asm/arch-tegra/warmboot.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /*
  26  * This is the place in SRAM where the SDRAM parameters are stored. There
  27  * are 4 blocks, one for each RAM code
  28  */
  29 #define SDRAM_PARAMS_BASE       (NV_PA_BASE_SRAM + 0x188)
  30
  31 /* TODO: If we later add support for the Misc GP controller, refactor this */
  32 union xm2cfga_reg {
  33         struct {
  34                 u32 reserved0:2;
  35                 u32 hsm_en:1;
  36                 u32 reserved1:2;
  37                 u32 preemp_en:1;
  38                 u32 vref_en:1;
  39                 u32 reserved2:5;
  40                 u32 cal_drvdn:5;
  41                 u32 reserved3:3;
  42                 u32 cal_drvup:5;
  43                 u32 reserved4:3;
  44                 u32 cal_drvdn_slwr:2;
  45                 u32 cal_drvup_slwf:2;
  46         };
  47         u32 word;
  48 };
  49
  50 union xm2cfgd_reg {
  51         struct {
  52                 u32 reserved0:2;
  53                 u32 hsm_en:1;
  54                 u32 schmt_en:1;
  55                 u32 lpmd:2;
  56                 u32 vref_en:1;
  57                 u32 reserved1:5;
  58                 u32 cal_drvdn:5;
  59                 u32 reserved2:3;
  60                 u32 cal_drvup:5;
  61                 u32 reserved3:3;
  62                 u32 cal_drvdn_slwr:2;
  63                 u32 cal_drvup_slwf:2;
  64         };
  65         u32 word;
  66 };
  67
  68 /*
  69  * TODO: This register is not documented in the TRM yet. We could move this
  70  * into the EMC and give it a proper interface, but not while it is
  71  * undocumented.
  72  */
  73 union fbio_spare_reg {
  74         struct {
  75                 u32 reserved:24;
  76                 u32 cfg_wb0:8;
  77         };
  78         u32 word;
  79 };
  80
  81 /* We pack the resume information into these unions for later */
  82 union scratch2_reg {
  83         struct {
  84                 u32 pllm_base_divm:5;
  85                 u32 pllm_base_divn:10;
  86                 u32 pllm_base_divp:3;
  87                 u32 pllm_misc_lfcon:4;
  88                 u32 pllm_misc_cpcon:4;
  89                 u32 gp_xm2cfga_padctrl_preemp:1;
  90                 u32 gp_xm2cfgd_padctrl_schmt:1;
  91                 u32 osc_ctrl_xobp:1;
  92                 u32 memory_type:3;
  93         };
  94         u32 word;
  95 };
  96
  97 union scratch4_reg {
  98         struct {
  99                 u32 emc_clock_divider:8;
 100                 u32 pllm_stable_time:8;
 101                 u32 pllx_stable_time:8;
 102                 u32 emc_fbio_spare_cfg_wb0:8;
 103         };
 104         u32 word;
 105 };
 106
 107 union scratch24_reg {
 108         struct {
 109                 u32 emc_auto_cal_wait:8;
 110                 u32 emc_pin_program_wait:8;
 111                 u32 warmboot_wait:8;
 112                 u32 reserved:8;
 113         };
 114         u32 word;
 115 };
 116
 117 int warmboot_save_sdram_params(void)
 118 {
 119         u32 ram_code;
 120         struct sdram_params sdram;
 121         struct apb_misc_pp_ctlr *apb_misc =
 122                                 (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
 123         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 124         struct apb_misc_gp_ctlr *gp =
 125                         (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 126         struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
 127         union scratch2_reg scratch2;
 128         union scratch4_reg scratch4;
 129         union scratch24_reg scratch24;
 130         union xm2cfga_reg xm2cfga;
 131         union xm2cfgd_reg xm2cfgd;
 132         union fbio_spare_reg fbio_spare;
 133
 134         /* get ram code that is used as index to array sdram_params in BCT */
 135         ram_code = (readl(&apb_misc->strapping_opt_a) >>
 136                           STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
 137         memcpy(&sdram,
 138                (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
 139                sizeof(sdram));
 140
 141         xm2cfga.word = readl(&gp->xm2cfga);
 142         xm2cfgd.word = readl(&gp->xm2cfgd);
 143
 144         scratch2.word = 0;
 145         scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
 146
 147         /* Get the memory PLL settings */
 148         {
 149                 u32 divm, divn, divp, cpcon, lfcon;
 150
 151                 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
 152                                         &cpcon, &lfcon))
 153                         return -1;
 154                 scratch2.pllm_base_divm = divm;
 155                 scratch2.pllm_base_divn = divn;
 156                 scratch2.pllm_base_divp = divp;
 157                 scratch2.pllm_misc_cpcon = cpcon;
 158                 scratch2.pllm_misc_lfcon = lfcon;
 159         }
 160
 161         scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
 162         scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
 163         scratch2.memory_type = sdram.memory_type;
 164         writel(scratch2.word, &pmc->pmc_scratch2);
 165
 166         /* collect data from various sources for pmc_scratch4 */
 167         fbio_spare.word = readl(&emc->fbio_spare);
 168         scratch4.word = 0;
 169         scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
 170         scratch4.emc_clock_divider = sdram.emc_clock_divider;
 171         scratch4.pllm_stable_time = -1;
 172         scratch4.pllx_stable_time = -1;
 173         writel(scratch4.word, &pmc->pmc_scratch4);
 174
 175         /* collect various data from sdram for pmc_scratch24 */
 176         scratch24.word = 0;
 177         scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
 178         scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
 179         scratch24.warmboot_wait = sdram.warm_boot_wait;
 180         writel(scratch24.word, &pmc->pmc_scratch24);
 181
 182         return 0;
 183 }
 184
 185 static u32 get_major_version(void)
 186 {
 187         u32 major_id;
 188         struct apb_misc_gp_ctlr *gp =
 189                 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 190
 191         major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
 192                         HIDREV_MAJORPREV_SHIFT;
 193         return major_id;
 194 }
 195
 196 static int is_production_mode_fuse_set(struct fuse_regs *fuse)
 197 {
 198         return readl(&fuse->production_mode);
 199 }
 200
 201 static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
 202 {
 203         return readl(&fuse->security_mode);
 204 }
 205
 206 static int is_failure_analysis_mode(struct fuse_regs *fuse)
 207 {
 208         return readl(&fuse->fa);
 209 }
 210
 211 static int ap20_is_odm_production_mode(void)
 212 {
 213         struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 214
 215         if (!is_failure_analysis_mode(fuse) &&
 216             is_odm_production_mode_fuse_set(fuse))
 217                 return 1;
 218         else
 219                 return 0;
 220 }
 221
 222 static int ap20_is_production_mode(void)
 223 {
 224         struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 225
 226         if (get_major_version() == 0)
 227                 return 1;
 228
 229         if (!is_failure_analysis_mode(fuse) &&
 230             is_production_mode_fuse_set(fuse) &&
 231             !is_odm_production_mode_fuse_set(fuse))
 232                 return 1;
 233         else
 234                 return 0;
 235 }
 236
 237 static enum fuse_operating_mode fuse_get_operation_mode(void)
 238 {
 239         u32 chip_id;
 240         struct apb_misc_gp_ctlr *gp =
 241                 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 242
 243         chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
 244                         HIDREV_CHIPID_SHIFT;
 245         if (chip_id == CHIPID_TEGRA20) {
 246                 if (ap20_is_odm_production_mode()) {
 247                         printf("!! odm_production_mode is not supported !!\n");
 248                         return MODE_UNDEFINED;
 249                 } else
 250                         if (ap20_is_production_mode())
 251                                 return MODE_PRODUCTION;
 252                         else
 253                                 return MODE_UNDEFINED;
 254         }
 255         return MODE_UNDEFINED;
 256 }
 257
 258 static void determine_crypto_options(int *is_encrypted, int *is_signed,
 259                                      int *use_zero_key)
 260 {
 261         switch (fuse_get_operation_mode()) {
 262         case MODE_PRODUCTION:
 263                 *is_encrypted = 0;
 264                 *is_signed = 1;
 265                 *use_zero_key = 1;
 266                 break;
 267         case MODE_UNDEFINED:
 268         default:
 269                 *is_encrypted = 0;
 270                 *is_signed = 0;
 271                 *use_zero_key  = 0;
 272                 break;
 273         }
 274 }
 275
 276 static int sign_wb_code(u32 start, u32 length, int use_zero_key)
 277 {
 278         int err;
 279         u8 *source;             /* Pointer to source */
 280         u8 *hash;
 281
 282         /* Calculate AES block parameters. */
 283         source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
 284         length -= offsetof(struct wb_header, random_aes_block);
 285         hash = (u8 *)(start + offsetof(struct wb_header, hash));
 286         err = sign_data_block(source, length, hash);
 287
 288         return err;
 289 }
 290
 291 int warmboot_prepare_code(u32 seg_address, u32 seg_length)
 292 {
 293         int err = 0;
 294         u32 length;                     /* length of the signed/encrypt code */
 295         struct wb_header *dst_header;   /* Pointer to dest WB header */
 296         int is_encrypted;               /* Segment is encrypted */
 297         int is_signed;                  /* Segment is signed */
 298         int use_zero_key;               /* Use key of all zeros */
 299
 300         /* Determine crypto options. */
 301         determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
 302
 303         /* Get the actual code limits. */
 304         length = roundup(((u32)wb_end - (u32)wb_start), 16);
 305
 306         /*
 307          * The region specified by seg_address must be in SDRAM and must be
 308          * nonzero in length.
 309          */
 310         if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
 311                 seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
 312                 err = -EFAULT;
 313                 goto fail;
 314         }
 315
 316         /* Things must be 16-byte aligned. */
 317         if ((seg_length & 0xF) || (seg_address & 0xF)) {
 318                 err = -EINVAL;
 319                 goto fail;
 320         }
 321
 322         /* Will the code fit? (destination includes wb_header + wb code) */
 323         if (seg_length < (length + sizeof(struct wb_header))) {
 324                 err = -EINVAL;
 325                 goto fail;
 326         }
 327
 328         dst_header = (struct wb_header *)seg_address;
 329         memset((char *)dst_header, 0, sizeof(struct wb_header));
 330
 331         /* Populate the random_aes_block as requested. */
 332         {
 333                 u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
 334                 u32 *end = (u32 *)(((u32)aes_block) +
 335                                    sizeof(dst_header->random_aes_block));
 336
 337                 do {
 338                         *aes_block++ = 0;
 339                 } while (aes_block < end);
 340         }
 341
 342         /* Populate the header. */
 343         dst_header->length_insecure = length + sizeof(struct wb_header);
 344         dst_header->length_secure = length + sizeof(struct wb_header);
 345         dst_header->destination = NV_WB_RUN_ADDRESS;
 346         dst_header->entry_point = NV_WB_RUN_ADDRESS;
 347         dst_header->code_length = length;
 348
 349         if (is_encrypted) {
 350                 printf("!!!! Encryption is not supported !!!!\n");
 351                 dst_header->length_insecure = 0;
 352                 err = -EACCES;
 353                 goto fail;
 354         } else
 355                 /* copy the wb code directly following dst_header. */
 356                 memcpy((char *)(dst_header+1), (char *)wb_start, length);
 357
 358         if (is_signed)
 359                 err = sign_wb_code(seg_address, dst_header->length_insecure,
 360                                    use_zero_key);
 361
 362 fail:
 363         if (err)
 364                 printf("Warning: warmboot code copy failed (error=%d)\n", err);
 365
 366         return err;
 367 }