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1 | /* | |
2 | * Copyright (C) 2015 Thomas Chou <[email protected]> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <dm.h> | |
9 | #include <dm/lists.h> | |
10 | #include <dm/device-internal.h> | |
11 | #include <clk.h> | |
12 | #include <errno.h> | |
13 | #include <timer.h> | |
14 | ||
15 | DECLARE_GLOBAL_DATA_PTR; | |
16 | ||
17 | /* | |
18 | * Implement a timer uclass to work with lib/time.c. The timer is usually | |
19 | * a 32/64 bits free-running up counter. The get_rate() method is used to get | |
20 | * the input clock frequency of the timer. The get_count() method is used | |
21 | * to get the current 64 bits count value. If the hardware is counting down, | |
22 | * the value should be inversed inside the method. There may be no real | |
23 | * tick, and no timer interrupt. | |
24 | */ | |
25 | ||
26 | int notrace timer_get_count(struct udevice *dev, u64 *count) | |
27 | { | |
28 | const struct timer_ops *ops = device_get_ops(dev); | |
29 | ||
30 | if (!ops->get_count) | |
31 | return -ENOSYS; | |
32 | ||
33 | return ops->get_count(dev, count); | |
34 | } | |
35 | ||
36 | unsigned long notrace timer_get_rate(struct udevice *dev) | |
37 | { | |
38 | struct timer_dev_priv *uc_priv = dev->uclass_priv; | |
39 | ||
40 | return uc_priv->clock_rate; | |
41 | } | |
42 | ||
43 | static int timer_pre_probe(struct udevice *dev) | |
44 | { | |
45 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); | |
46 | struct clk timer_clk; | |
47 | int err; | |
48 | ulong ret; | |
49 | ||
50 | err = clk_get_by_index(dev, 0, &timer_clk); | |
51 | if (!err) { | |
52 | ret = clk_get_rate(&timer_clk); | |
53 | if (IS_ERR_VALUE(ret)) | |
54 | return ret; | |
55 | uc_priv->clock_rate = ret; | |
56 | } else | |
57 | uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob, | |
58 | dev_of_offset(dev), "clock-frequency", 0); | |
59 | ||
60 | return 0; | |
61 | } | |
62 | ||
63 | static int timer_post_probe(struct udevice *dev) | |
64 | { | |
65 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); | |
66 | ||
67 | if (!uc_priv->clock_rate) | |
68 | return -EINVAL; | |
69 | ||
70 | return 0; | |
71 | } | |
72 | ||
73 | u64 timer_conv_64(u32 count) | |
74 | { | |
75 | /* increment tbh if tbl has rolled over */ | |
76 | if (count < gd->timebase_l) | |
77 | gd->timebase_h++; | |
78 | gd->timebase_l = count; | |
79 | return ((u64)gd->timebase_h << 32) | gd->timebase_l; | |
80 | } | |
81 | ||
82 | int notrace dm_timer_init(void) | |
83 | { | |
84 | const void *blob = gd->fdt_blob; | |
85 | struct udevice *dev = NULL; | |
86 | int node; | |
87 | int ret; | |
88 | ||
89 | if (gd->timer) | |
90 | return 0; | |
91 | ||
92 | /* Check for a chosen timer to be used for tick */ | |
93 | node = fdtdec_get_chosen_node(blob, "tick-timer"); | |
94 | if (node < 0) { | |
95 | /* No chosen timer, trying first available timer */ | |
96 | ret = uclass_first_device_err(UCLASS_TIMER, &dev); | |
97 | if (ret) | |
98 | return ret; | |
99 | } else { | |
100 | if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, &dev)) { | |
101 | /* | |
102 | * If the timer is not marked to be bound before | |
103 | * relocation, bind it anyway. | |
104 | */ | |
105 | if (node > 0 && | |
106 | !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node), | |
107 | &dev)) { | |
108 | ret = device_probe(dev); | |
109 | if (ret) | |
110 | return ret; | |
111 | } | |
112 | } | |
113 | } | |
114 | ||
115 | if (dev) { | |
116 | gd->timer = dev; | |
117 | return 0; | |
118 | } | |
119 | ||
120 | return -ENODEV; | |
121 | } | |
122 | ||
123 | UCLASS_DRIVER(timer) = { | |
124 | .id = UCLASS_TIMER, | |
125 | .name = "timer", | |
126 | .pre_probe = timer_pre_probe, | |
127 | .flags = DM_UC_FLAG_SEQ_ALIAS, | |
128 | .post_probe = timer_post_probe, | |
129 | .per_device_auto_alloc_size = sizeof(struct timer_dev_priv), | |
130 | }; |