Git Repo - u-boot.git/blame_incremental - arch/arm/mach-versal-net/cpu.c

... / ...

Commit	Line	Data
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2021 - 2022, Xilinx, Inc.
	4	* Copyright (C) 2022, Advanced Micro Devices, Inc.
	5	*
	6	* Michal Simek <[email protected]>
	7	*/
	8
	9	#include <init.h>
	10	#include <asm/armv8/mmu.h>
	11	#include <asm/cache.h>
	12	#include <asm/global_data.h>
	13	#include <asm/io.h>
	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/cache.h>
	17	#include <dm/platdata.h>
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	#define VERSAL_NET_MEM_MAP_USED 5
	22
	23	#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
	24
	25	/* +1 is end of list which needs to be empty */
	26	#define VERSAL_NET_MEM_MAP_MAX (VERSAL_NET_MEM_MAP_USED + DRAM_BANKS + 1)
	27
	28	static struct mm_region versal_mem_map[VERSAL_NET_MEM_MAP_MAX] = {
	29	{
	30	.virt = 0x80000000UL,
	31	.phys = 0x80000000UL,
	32	.size = 0x70000000UL,
	33	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	34	PTE_BLOCK_NON_SHARE \|
	35	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	36	}, {
	37	.virt = 0xf0000000UL,
	38	.phys = 0xf0000000UL,
	39	.size = 0x0fe00000UL,
	40	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	41	PTE_BLOCK_NON_SHARE \|
	42	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	43	}, {
	44	.virt = 0x400000000UL,
	45	.phys = 0x400000000UL,
	46	.size = 0x200000000UL,
	47	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	48	PTE_BLOCK_NON_SHARE \|
	49	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	50	}, {
	51	.virt = 0x600000000UL,
	52	.phys = 0x600000000UL,
	53	.size = 0x800000000UL,
	54	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	55	PTE_BLOCK_INNER_SHARE
	56	}, {
	57	.virt = 0xe00000000UL,
	58	.phys = 0xe00000000UL,
	59	.size = 0xf200000000UL,
	60	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	61	PTE_BLOCK_NON_SHARE \|
	62	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	63	}
	64	};
	65
	66	void mem_map_fill(void)
	67	{
	68	int banks = VERSAL_NET_MEM_MAP_USED;
	69
	70	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	71	/* Zero size means no more DDR that's this is end */
	72	if (!gd->bd->bi_dram[i].size)
	73	break;
	74
	75	versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
	76	versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
	77	versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
	78	versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	79	PTE_BLOCK_INNER_SHARE;
	80	banks = banks + 1;
	81	}
	82	}
	83
	84	struct mm_region *mem_map = versal_mem_map;
	85
	86	u64 get_page_table_size(void)
	87	{
	88	return 0x14000;
	89	}
	90
	91	U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
	92	.name = "soc_xilinx_versal_net",
	93	};