projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 3225f34e BS |
2 | /* |
| 3 | * Configuation settings for the SAMA5D3xEK board. | |
| 4 | * | |
| 5 | * Copyright (C) 2012 - 2013 Atmel | |
| 6 | * | |
| 7 | * based on at91sam9m10g45ek.h by: | |
| 8 | * Stelian Pop <[email protected]> | |
| 9 | * Lead Tech Design <www.leadtechdesign.com> | |
| 3225f34e BS |
10 | */ |
| 11 | ||
| 12 | #ifndef __CONFIG_H | |
| 13 | #define __CONFIG_H | |
| 14 | ||
| b2d387bc | 15 | #include "at91-sama5_common.h" |
| 3225f34e | 16 | |
| 3225f34e BS |
17 | /* |
| 18 | * This needs to be defined for the OHCI code to work but it is defined as | |
| 19 | * ATMEL_ID_UHPHS in the CPU specific header files. | |
| 20 | */ | |
| e61ed48f | 21 | #define ATMEL_ID_UHP 32 |
| 3225f34e BS |
22 | |
| 23 | /* | |
| 24 | * Specify the clock enable bit in the PMC_SCER register. | |
| 25 | */ | |
| e61ed48f | 26 | #define ATMEL_PMC_UHP (1 << 6) |
| 3225f34e | 27 | |
| d6b79434 | 28 | /* NOR flash */ |
| e856bdcf | 29 | #ifdef CONFIG_MTD_NOR_FLASH |
| 65cc0e2a | 30 | #define CFG_SYS_FLASH_BASE 0x10000000 |
| d6b79434 | 31 | #endif |
| 3225f34e | 32 | |
| 3225f34e | 33 | /* SDRAM */ |
| aa6e94de TR |
34 | #define CFG_SYS_SDRAM_BASE 0x20000000 |
| 35 | #define CFG_SYS_SDRAM_SIZE 0x20000000 | |
| 3225f34e | 36 | |
| 3225f34e | 37 | /* SerialFlash */ |
| 3225f34e | 38 | |
| 3225f34e | 39 | /* NAND flash */ |
| 3225f34e | 40 | #ifdef CONFIG_CMD_NAND |
| 4e590945 | 41 | #define CFG_SYS_NAND_BASE 0x60000000 |
| 3225f34e | 42 | /* our ALE is AD21 */ |
| 4e590945 | 43 | #define CFG_SYS_NAND_MASK_ALE (1 << 21) |
| 3225f34e | 44 | /* our CLE is AD22 */ |
| 4e590945 | 45 | #define CFG_SYS_NAND_MASK_CLE (1 << 22) |
| 8f1a80e9 | 46 | #endif |
| 3225f34e | 47 | |
| c5e8885a | 48 | /* SPL */ |
| c5e8885a | 49 | |
| 3225f34e | 50 | #endif |