]> Git Repo - u-boot.git/blame - drivers/clk/renesas/clk-rcar-gen3.c
projects / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'xilinx-for-v2025.04-rc2' of https://source.denx.de/u-boot/custodians/u...
[u-boot.git] / drivers / clk / renesas / clk-rcar-gen3.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
36c2ee4c 2/*
d774197b 3 * Renesas R-Car Gen3 CPG MSSR driver
36c2ee4c
MV		 4 *
5 * Copyright (C) 2017 Marek Vasut <[email protected]>
6 *
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 *
10 * Copyright (C) 2016 Glider bvba
36c2ee4c
MV		 11 */
12
36c2ee4c
MV		 13#include <clk-uclass.h>
14#include <dm.h>
326e05c5
MV		 15#include <dm/device-internal.h>
16#include <dm/lists.h>
36c2ee4c 17#include <errno.h>
f7ae49fc 18#include <log.h>
36c2ee4c 19#include <wait_bit.h>
401d1c4f 20#include <asm/global_data.h>
36c2ee4c 21#include <asm/io.h>
a1ec0bbc 22#include <linux/bitfield.h>
cd93d625 23#include <linux/bitops.h>
d48c38db 24#include <linux/clk-provider.h>
326e05c5 25#include <reset-uclass.h>
36c2ee4c 26
f77b5a4c
MV		 27#include <dt-bindings/clock/renesas-cpg-mssr.h>
28
29#include "renesas-cpg-mssr.h"
d2628671 30#include "rcar-gen3-cpg.h"
1b4ca865 31#include "rcar-cpg-lib.h"
36c2ee4c 32
36c2ee4c
MV		 33#define CPG_PLL0CR 0x00d8
34#define CPG_PLL2CR 0x002c
35#define CPG_PLL4CR 0x01f4
36
3e01ed8e
MV		 37#define SD0CKCR1 0x08a4
38
39static const struct clk_div_table gen3_cpg_rpcsrc_div_table[] = {
a1ec0bbc
HP		 40 { 2, 5 }, { 3, 6 }, { 0, 0 },
41};
42
3e01ed8e
MV		 43static const struct clk_div_table gen4_cpg_rpcsrc_div_table[] = {
44 { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
45};
46
d8132ae3
HP		 47static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
48 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
49 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
50 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
51};
52
53static const struct clk_div_table r8a77970_cpg_sd0_div_table[] = {
54 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
55 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
56 { 0, 0 },
57};
58
716d7752
MV		 59static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
60 struct cpg_mssr_info *info, struct clk *parent)
61{
62 const struct cpg_core_clk *core;
99c7e031 63 u8 shift;
716d7752
MV		 64 int ret;
65
66 if (!renesas_clk_is_mod(clk)) {
67 ret = renesas_clk_get_core(clk, info, &core);
68 if (ret)
69 return ret;
70
72242e54 71 if (core->type == CLK_TYPE_GEN3_MDSEL) {
dd4d130c 72 shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
716d7752 73 parent->dev = clk->dev;
99c7e031 74 parent->id = core->parent >> shift;
716d7752
MV		 75 parent->id &= 0xffff;
76 return 0;
77 }
78 }
79
80 return renesas_clk_get_parent(clk, info, parent);
81}
82
4dbbc3f3
HP		 83static int gen3_clk_enable(struct clk *clk)
84{
85 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
86
87 return renesas_clk_endisable(clk, priv->base, priv->info, true);
88}
89
90static int gen3_clk_disable(struct clk *clk)
91{
92 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
93
94 return renesas_clk_endisable(clk, priv->base, priv->info, false);
95}
96
97static u64 gen3_clk_get_rate64(struct clk *clk);
98
f58d6771 99static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
4b20eef3
MV		 100{
101 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
d2628671 102 struct cpg_mssr_info *info = priv->info;
4b20eef3 103 const struct cpg_core_clk *core;
4dbbc3f3 104 struct clk parent, grandparent;
4b20eef3 105 int ret;
4dbbc3f3
HP		 106
107 /*
108 * The clk may be either CPG_MOD or core clock, in case this is MOD
109 * clock, use core clock one level up, otherwise use the clock as-is.
110 * Note that parent clock here always represents core clock. Also note
111 * that grandparent clock are the parent clock of the core clock here.
112 */
113 if (renesas_clk_is_mod(clk)) {
114 ret = gen3_clk_get_parent(priv, clk, info, &parent);
115 if (ret) {
116 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
117 return ret;
118 }
119 } else {
120 parent = *clk;
4b20eef3
MV		 121 }
122
d2628671 123 if (renesas_clk_is_mod(&parent))
4b20eef3
MV		 124 return 0;
125
d2628671 126 ret = renesas_clk_get_core(&parent, info, &core);
4b20eef3
MV		 127 if (ret)
128 return ret;
129
4dbbc3f3
HP		 130 ret = renesas_clk_get_parent(&parent, info, &grandparent);
131 if (ret) {
132 printf("%s[%i] grandparent fail, ret=%i\n", __func__, __LINE__, ret);
133 return ret;
134 }
4b20eef3 135
4dbbc3f3
HP		 136 switch (core->type) {
137 case CLK_TYPE_GEN3_SDH:
138 fallthrough;
139 case CLK_TYPE_GEN4_SDH:
1b4ca865
HP		 140 return rcar_clk_set_rate64_sdh(core->parent,
141 gen3_clk_get_rate64(&grandparent),
142 rate, priv->base + core->offset);
4b20eef3 143
4dbbc3f3
HP		 144 case CLK_TYPE_GEN3_SD:
145 fallthrough;
146 case CLK_TYPE_GEN4_SD:
1b4ca865
HP		 147 return rcar_clk_set_rate64_sd(core->parent,
148 gen3_clk_get_rate64(&grandparent),
149 rate, priv->base + core->offset);
d8132ae3
HP		 150
151 case CLK_TYPE_R8A77970_SD0:
1b4ca865
HP		 152 return rcar_clk_set_rate64_div_table(core->parent,
153 gen3_clk_get_rate64(&grandparent),
154 rate, priv->base + core->offset,
155 CPG_SDCKCR_SD0FC_MASK,
156 r8a77970_cpg_sd0_div_table, "SD");
4dbbc3f3 157 }
d2628671 158
4dbbc3f3 159 return 0;
36c2ee4c
MV		 160}
161
e7690e61
MV		 162static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
163 struct clk *parent,
e7690e61
MV		 164 u32 mul_reg, u32 mult, u32 div,
165 char *name)
166{
167 u32 value;
168 u64 rate;
169
170 if (mul_reg) {
171 value = readl(priv->base + mul_reg);
172 mult = (((value >> 24) & 0x7f) + 1) * 2;
173 div = 1;
174 }
175
176 rate = (gen3_clk_get_rate64(parent) * mult) / div;
177
a61a8241
MV		 178 debug("%s[%i] %s clk: mult=%u div=%u => rate=%llu\n",
179 __func__, __LINE__, name, mult, div, rate);
e7690e61
MV		 180 return rate;
181}
182
8376e0e6 183static u64 gen3_clk_get_rate64(struct clk *clk)
36c2ee4c
MV		 184{
185 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
f11c9679 186 struct cpg_mssr_info *info = priv->info;
36c2ee4c
MV		 187 struct clk parent;
188 const struct cpg_core_clk *core;
3e01ed8e
MV		 189 const struct rcar_gen3_cpg_pll_config *gen3_pll_config =
190 priv->gen3_cpg_pll_config;
191 const struct rcar_gen4_cpg_pll_config *gen4_pll_config =
192 priv->gen4_cpg_pll_config;
a1ec0bbc 193 u32 value, div;
8376e0e6 194 u64 rate = 0;
99c7e031 195 u8 shift;
4dbbc3f3 196 int ret;
36c2ee4c
MV		 197
198 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
199
716d7752 200 ret = gen3_clk_get_parent(priv, clk, info, &parent);
36c2ee4c
MV		 201 if (ret) {
202 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
203 return ret;
204 }
205
d2628671 206 if (renesas_clk_is_mod(clk)) {
8376e0e6
MV		 207 rate = gen3_clk_get_rate64(&parent);
208 debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
36c2ee4c
MV		 209 __func__, __LINE__, parent.id, rate);
210 return rate;
211 }
212
d2628671 213 ret = renesas_clk_get_core(clk, info, &core);
36c2ee4c
MV		 214 if (ret)
215 return ret;
216
217 switch (core->type) {
218 case CLK_TYPE_IN:
f11c9679 219 if (core->id == info->clk_extal_id) {
36c2ee4c 220 rate = clk_get_rate(&priv->clk_extal);
8376e0e6 221 debug("%s[%i] EXTAL clk: rate=%llu\n",
36c2ee4c
MV		 222 __func__, __LINE__, rate);
223 return rate;
224 }
225
f11c9679 226 if (core->id == info->clk_extalr_id) {
36c2ee4c 227 rate = clk_get_rate(&priv->clk_extalr);
8376e0e6 228 debug("%s[%i] EXTALR clk: rate=%llu\n",
36c2ee4c
MV		 229 __func__, __LINE__, rate);
230 return rate;
231 }
232
233 return -EINVAL;
234
235 case CLK_TYPE_GEN3_MAIN:
a61a8241 236 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
3e01ed8e 237 0, 1, gen3_pll_config->extal_div,
e7690e61 238 "MAIN");
36c2ee4c
MV		 239
240 case CLK_TYPE_GEN3_PLL0:
a61a8241 241 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
e7690e61 242 CPG_PLL0CR, 0, 0, "PLL0");
36c2ee4c
MV		 243
244 case CLK_TYPE_GEN3_PLL1:
a61a8241 245 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
3e01ed8e
MV		 246 0, gen3_pll_config->pll1_mult,
247 gen3_pll_config->pll1_div,
248 "PLL1");
36c2ee4c
MV		 249
250 case CLK_TYPE_GEN3_PLL2:
a61a8241 251 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
e7690e61 252 CPG_PLL2CR, 0, 0, "PLL2");
36c2ee4c
MV		 253
254 case CLK_TYPE_GEN3_PLL3:
a61a8241 255 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
3e01ed8e
MV		 256 0, gen3_pll_config->pll3_mult,
257 gen3_pll_config->pll3_div,
258 "PLL3");
36c2ee4c
MV		 259
260 case CLK_TYPE_GEN3_PLL4:
a61a8241 261 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
e7690e61 262 CPG_PLL4CR, 0, 0, "PLL4");
36c2ee4c 263
733da621 264 case CLK_TYPE_GEN4_MAIN:
a61a8241 265 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
3e01ed8e
MV		 266 0, 1, gen4_pll_config->extal_div,
267 "MAIN");
44c78aa7 268
733da621 269 case CLK_TYPE_GEN4_PLL1:
a61a8241 270 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
3e01ed8e
MV		 271 0, gen4_pll_config->pll1_mult,
272 gen4_pll_config->pll1_div,
273 "PLL1");
274
275 case CLK_TYPE_GEN4_PLL2:
276 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
277 0, gen4_pll_config->pll2_mult,
278 gen4_pll_config->pll2_div,
279 "PLL2");
44c78aa7 280
733da621 281 case CLK_TYPE_GEN4_PLL2X_3X:
a61a8241 282 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
3e01ed8e
MV		 283 core->offset, 0, 0, "PLL2X_3X");
284
285 case CLK_TYPE_GEN4_PLL3:
286 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
287 0, gen4_pll_config->pll3_mult,
288 gen4_pll_config->pll3_div,
289 "PLL3");
290
291 case CLK_TYPE_GEN4_PLL4:
292 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
293 0, gen4_pll_config->pll4_mult,
294 gen4_pll_config->pll4_div,
295 "PLL4");
44c78aa7 296
733da621 297 case CLK_TYPE_GEN4_PLL5:
a61a8241 298 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
3e01ed8e
MV		 299 0, gen4_pll_config->pll5_mult,
300 gen4_pll_config->pll5_div,
301 "PLL5");
302
303 case CLK_TYPE_GEN4_PLL6:
304 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
305 0, gen4_pll_config->pll6_mult,
306 gen4_pll_config->pll6_div,
307 "PLL6");
44c78aa7 308
0fb76cc0
MV		 309 case CLK_TYPE_GEN4_PLL7:
310 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
311 0, gen4_pll_config->pll7_mult,
312 gen4_pll_config->pll7_div,
313 "PLL7");
314
36c2ee4c 315 case CLK_TYPE_FF:
a61a8241 316 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
e7690e61
MV		 317 0, core->mult, core->div,
318 "FIXED");
36c2ee4c 319
72242e54 320 case CLK_TYPE_GEN3_MDSEL:
dd4d130c 321 shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
99c7e031 322 div = (core->div >> shift) & 0xffff;
716d7752
MV		 323 rate = gen3_clk_get_rate64(&parent) / div;
324 debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
99c7e031 325 __func__, __LINE__, (core->parent >> shift) & 0xffff,
716d7752
MV		 326 div, rate);
327 return rate;
328
3e01ed8e
MV		 329 case CLK_TYPE_GEN4_SDSRC:
330 div = ((readl(priv->base + SD0CKCR1) >> 29) & 0x03) + 4;
331 rate = gen3_clk_get_rate64(&parent) / div;
332 debug("%s[%i] SDSRC clk: parent=%i div=%u => rate=%llu\n",
333 __func__, __LINE__, core->parent, div, rate);
334 return rate;
335
c206dfd2 336 case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
733da621
MV		 337 fallthrough;
338 case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
1b4ca865
HP		 339 return rcar_clk_get_rate64_sdh(core->parent,
340 gen3_clk_get_rate64(&parent),
341 priv->base + core->offset);
c206dfd2 342
d8132ae3
HP		 343 case CLK_TYPE_R8A77970_SD0H:
344 return rcar_clk_get_rate64_div_table(core->parent,
345 gen3_clk_get_rate64(&parent),
346 priv->base + core->offset,
347 CPG_SDCKCR_SDHFC_MASK,
348 r8a77970_cpg_sd0h_div_table, "SDH");
349
4dbbc3f3 350 case CLK_TYPE_GEN3_SD:
44c78aa7 351 fallthrough;
733da621 352 case CLK_TYPE_GEN4_SD:
1b4ca865
HP		 353 return rcar_clk_get_rate64_sd(core->parent,
354 gen3_clk_get_rate64(&parent),
355 priv->base + core->offset);
849ab0a6 356
d8132ae3
HP		 357 case CLK_TYPE_R8A77970_SD0:
358 return rcar_clk_get_rate64_div_table(core->parent,
359 gen3_clk_get_rate64(&parent),
360 priv->base + core->offset,
361 CPG_SDCKCR_SD0FC_MASK,
362 r8a77970_cpg_sd0_div_table, "SD");
363
a1ec0bbc
HP		 364 case CLK_TYPE_GEN3_RPCSRC:
365 return rcar_clk_get_rate64_div_table(core->parent,
366 gen3_clk_get_rate64(&parent),
367 priv->base + CPG_RPCCKCR,
368 CPG_RPCCKCR_DIV_POST_MASK,
3e01ed8e
MV		 369 gen3_cpg_rpcsrc_div_table,
370 "RPCSRC");
371
372 case CLK_TYPE_GEN4_RPCSRC:
373 return rcar_clk_get_rate64_div_table(core->parent,
374 gen3_clk_get_rate64(&parent),
375 priv->base + CPG_RPCCKCR,
376 CPG_RPCCKCR_DIV_POST_MASK,
377 gen4_cpg_rpcsrc_div_table,
378 "RPCSRC");
a1ec0bbc 379
c287c184
HP		 380 case CLK_TYPE_GEN3_D3_RPCSRC:
381 case CLK_TYPE_GEN3_E3_RPCSRC:
382 /*
383 * Register RPCSRC as fixed factor clock based on the
384 * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
385 * which has been set prior to booting the kernel.
386 */
387 value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
388
389 switch (value) {
390 case 0:
391 div = 5;
392 break;
393 case 1:
394 div = 3;
395 break;
396 case 2:
397 div = core->div;
398 break;
399 case 3:
400 default:
401 div = 2;
402 break;
403 }
404
405 rate = gen3_clk_get_rate64(&parent) / div;
406 debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u => rate=%llu\n",
407 __func__, __LINE__, (core->parent >> 16) & 0xffff, div, rate);
408
409 return rate;
410
849ab0a6 411 case CLK_TYPE_GEN3_RPC:
733da621 412 case CLK_TYPE_GEN4_RPC:
1b4ca865
HP		 413 return rcar_clk_get_rate64_rpc(core->parent,
414 gen3_clk_get_rate64(&parent),
415 priv->base + CPG_RPCCKCR);
849ab0a6 416
a1ec0bbc
HP		 417 case CLK_TYPE_GEN3_RPCD2:
418 case CLK_TYPE_GEN4_RPCD2:
1b4ca865
HP		 419 return rcar_clk_get_rate64_rpcd2(core->parent,
420 gen3_clk_get_rate64(&parent));
849ab0a6 421
36c2ee4c
MV		 422 }
423
424 printf("%s[%i] unknown fail\n", __func__, __LINE__);
425
426 return -ENOENT;
427}
428
8376e0e6
MV		 429static ulong gen3_clk_get_rate(struct clk *clk)
430{
431 return gen3_clk_get_rate64(clk);
432}
433
36c2ee4c
MV		 434static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
435{
fd5577ce 436 /* Force correct SD-IF divider configuration if applicable */
f58d6771 437 gen3_clk_setup_sdif_div(clk, rate);
8376e0e6 438 return gen3_clk_get_rate64(clk);
36c2ee4c
MV		 439}
440
441static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
442{
443 if (args->args_count != 2) {
46ad7cef 444 debug("Invalid args_count: %d\n", args->args_count);
36c2ee4c
MV		 445 return -EINVAL;
446 }
447
448 clk->id = (args->args[0] << 16) | args->args[1];
449
450 return 0;
451}
452
f77b5a4c 453const struct clk_ops gen3_clk_ops = {
36c2ee4c
MV		 454 .enable = gen3_clk_enable,
455 .disable = gen3_clk_disable,
456 .get_rate = gen3_clk_get_rate,
457 .set_rate = gen3_clk_set_rate,
458 .of_xlate = gen3_clk_of_xlate,
459};
460
326e05c5 461static int gen3_clk_probe(struct udevice *dev)
36c2ee4c
MV		 462{
463 struct gen3_clk_priv *priv = dev_get_priv(dev);
f77b5a4c
MV		 464 struct cpg_mssr_info *info =
465 (struct cpg_mssr_info *)dev_get_driver_data(dev);
3e01ed8e 466 const void *pll_config;
36c2ee4c 467 fdt_addr_t rst_base;
36c2ee4c
MV		 468 int ret;
469
8613c8d8 470 priv->base = dev_read_addr_ptr(dev);
36c2ee4c
MV		 471 if (!priv->base)
472 return -EINVAL;
473
f77b5a4c
MV		 474 priv->info = info;
475 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
476 if (ret < 0)
477 return ret;
36c2ee4c
MV		 478
479 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
480 if (rst_base == FDT_ADDR_T_NONE)
481 return -EINVAL;
482
99c7e031 483 priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
36c2ee4c 484
3e01ed8e 485 pll_config = info->get_pll_config(priv->cpg_mode);
36c2ee4c 486
d413214f
HP		 487 if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
488 priv->info->status_regs = mstpsr;
489 priv->info->control_regs = smstpcr;
490 priv->info->reset_regs = srcr;
491 priv->info->reset_clear_regs = srstclr;
3e01ed8e
MV		 492 priv->gen3_cpg_pll_config = pll_config;
493 if (!priv->gen3_cpg_pll_config->extal_div)
494 return -EINVAL;
495 } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
496 priv->info->status_regs = mstpsr_for_gen4;
497 priv->info->control_regs = mstpcr_for_gen4;
498 priv->info->reset_regs = srcr_for_gen4;
499 priv->info->reset_clear_regs = srstclr_for_gen4;
500 priv->gen4_cpg_pll_config = pll_config;
501 if (!priv->gen4_cpg_pll_config->extal_div)
502 return -EINVAL;
d413214f
HP		 503 } else {
504 return -EINVAL;
505 }
506
36c2ee4c
MV		 507 ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
508 if (ret < 0)
509 return ret;
510
f77b5a4c
MV		 511 if (info->extalr_node) {
512 ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
2c150950
MV		 513 if (ret < 0)
514 return ret;
515 }
36c2ee4c
MV		 516
517 return 0;
518}
519
326e05c5 520static int gen3_clk_remove(struct udevice *dev)
18cac5af
MV		 521{
522 struct gen3_clk_priv *priv = dev_get_priv(dev);
18cac5af 523
d2628671 524 return renesas_clk_remove(priv->base, priv->info);
18cac5af 525}
326e05c5
MV		 526
527U_BOOT_DRIVER(clk_gen3) = {
528 .name = "clk_gen3",
529 .id = UCLASS_CLK,
530 .priv_auto = sizeof(struct gen3_clk_priv),
531 .ops = &gen3_clk_ops,
532 .probe = gen3_clk_probe,
533 .remove = gen3_clk_remove,
a2bd9954 534 .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
326e05c5
MV		 535};
536
537static int gen3_reset_assert(struct reset_ctl *reset_ctl)
538{
539 struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
540 struct gen3_clk_priv *priv = dev_get_priv(cdev);
afafaa2a
MV		 541 unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
542 unsigned int reg = packed_id / 32;
543 unsigned int bit = packed_id % 32;
326e05c5
MV		 544 u32 bitmask = BIT(bit);
545
546 writel(bitmask, priv->base + priv->info->reset_regs[reg]);
547
548 return 0;
549}
550
551static int gen3_reset_deassert(struct reset_ctl *reset_ctl)
552{
553 struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
554 struct gen3_clk_priv *priv = dev_get_priv(cdev);
afafaa2a
MV		 555 unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
556 unsigned int reg = packed_id / 32;
557 unsigned int bit = packed_id % 32;
326e05c5
MV		 558 u32 bitmask = BIT(bit);
559
560 writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]);
561
562 return 0;
563}
564
565static const struct reset_ops rst_gen3_ops = {
566 .rst_assert = gen3_reset_assert,
567 .rst_deassert = gen3_reset_deassert,
568};
569
570U_BOOT_DRIVER(rst_gen3) = {
571 .name = "rst_gen3",
572 .id = UCLASS_RESET,
573 .ops = &rst_gen3_ops,
a2bd9954 574 .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
326e05c5
MV		 575};
576
577int gen3_cpg_bind(struct udevice *parent)
578{
579 struct cpg_mssr_info *info =
580 (struct cpg_mssr_info *)dev_get_driver_data(parent);
581 struct udevice *cdev, *rdev;
c78a8139 582 struct driver *cdrv, *rdrv;
326e05c5
MV		 583 int ret;
584
c78a8139
MV		 585 cdrv = lists_driver_lookup_name("clk_gen3");
586 if (!cdrv)
326e05c5
MV		 587 return -ENOENT;
588
c78a8139
MV		 589
590 rdrv = lists_driver_lookup_name("rst_gen3");
591 if (!rdrv)
592 return -ENOENT;
593
594 ret = device_bind_with_driver_data(parent, cdrv, "clk_gen3", (ulong)info,
326e05c5
MV		 595 dev_ofnode(parent), &cdev);
596 if (ret)
597 return ret;
598
c78a8139 599 ret = device_bind_with_driver_data(parent, rdrv, "rst_gen3", (ulong)cdev,
326e05c5
MV		 600 dev_ofnode(parent), &rdev);
601 if (ret)
602 device_unbind(cdev);
603
604 return ret;
605}
Empty description
This page took 0.283285 seconds and 5 git commands to generate.