[u-boot.git] / board / freescale / ls1028a / ls1028a.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019 NXP
 */

#include <common.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
#include <fsl_ddr.h>
#include <net.h>
#include <asm/io.h>
#include <hwconfig.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <i2c.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
#include <fsl_immap.h>
#include <netdev.h>

#include <fdtdec.h>
#include <miiphy.h>
#include "../common/qixis.h"
#include "../drivers/net/fsl_enetc.h"

DECLARE_GLOBAL_DATA_PTR;

int config_board_mux(void)
{
#ifndef CONFIG_LPUART
#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
	u8 reg;

	reg = QIXIS_READ(brdcfg[13]);
	/* Field| Function
	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
	 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
	 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
	 */
	reg &= ~(0xf0);
	reg |= 0xb0;
	QIXIS_WRITE(brdcfg[13], reg);

	reg = QIXIS_READ(brdcfg[15]);
	/* Field| Function
	 * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
	 * CAN1 | 0= CAN #1 transceiver enabled
	 * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
	 * CAN2 | 0= CAN #2 transceiver enabled
	 */
	reg &= ~(0xc0);
	QIXIS_WRITE(brdcfg[15], reg);
#endif
#endif

	return 0;
}

#ifdef CONFIG_LPUART
u32 get_lpuart_clk(void)
{
	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
}
#endif

int board_init(void)
{
#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif

#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif

#ifndef CONFIG_SYS_EARLY_PCI_INIT
	pci_init();
#endif

#if defined(CONFIG_TARGET_LS1028ARDB)
	u8 val = I2C_MUX_CH_DEFAULT;

#ifndef CONFIG_DM_I2C
	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
#else
	struct udevice *dev;

	if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
		dm_i2c_write(dev, 0x0b, &val, 1);
#endif
#endif

#if defined(CONFIG_TARGET_LS1028ARDB)
	u8 reg;

	reg = QIXIS_READ(brdcfg[4]);
	/*
	 * Field | Function
	 * 3     | DisplayPort Power Enable (net DP_PWR_EN):
	 * DPPWR | 0= DP_PWR is enabled.
	 */
	reg &= ~(DP_PWD_EN_DEFAULT_MASK);
	QIXIS_WRITE(brdcfg[4], reg);
#endif
	return 0;
}

int board_eth_init(struct bd_info *bis)
{
	return pci_eth_init(bis);
}

#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
	config_board_mux();

	return 0;
}
#endif

int board_early_init_f(void)
{
#ifdef CONFIG_LPUART
	u8 uart;
#endif

#ifdef CONFIG_SYS_I2C_EARLY_INIT
	i2c_early_init_f();
#endif

	fsl_lsch3_early_init_f();

#ifdef CONFIG_LPUART
	/*
	 * Field| Function
	 * --------------------------------------------------------------
	 * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
	 * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
	 * --------------------------------------------------------------
	 * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
	 * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
	 */
	/* use lpuart0 as system console */
	uart = QIXIS_READ(brdcfg[13]);
	uart &= ~CFG_LPUART_MUX_MASK;
	uart |= CFG_LPUART_EN;
	QIXIS_WRITE(brdcfg[13], uart);
#endif

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
}

int esdhc_status_fixup(void *blob, const char *compat)
{
	void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
	char esdhc1_path[] = "/soc/mmc@2140000";
	char esdhc2_path[] = "/soc/mmc@2150000";
	char dspi1_path[] = "/soc/spi@2100000";
	char dspi2_path[] = "/soc/spi@2110000";
	u32 mux_sdhc1, mux_sdhc2;
	u32 io = 0;

	/*
	 * The PMUX IO-expander for mux select is used to control
	 * the muxing of various onboard interfaces.
	 */

	io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
	mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;

	/* Disable esdhc1/dspi1 if not selected. */
	if (mux_sdhc1 != 0)
		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
				 sizeof("disabled"), 1);
	if (mux_sdhc1 != 2)
		do_fixup_by_path(blob, dspi1_path, "status", "disabled",
				 sizeof("disabled"), 1);

	io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
	mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;

	/* Disable esdhc2/dspi2 if not selected. */
	if (mux_sdhc2 != 0)
		do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
				 sizeof("disabled"), 1);
	if (mux_sdhc2 != 2)
		do_fixup_by_path(blob, dspi2_path, "status", "disabled",
				 sizeof("disabled"), 1);

	return 0;
}

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

#ifdef CONFIG_RESV_RAM
	/* reduce size if reserved memory is within this bank */
	if (gd->arch.resv_ram >= base[0] &&
	    gd->arch.resv_ram < base[0] + size[0])
		size[0] = gd->arch.resv_ram - base[0];
	else if (gd->arch.resv_ram >= base[1] &&
		 gd->arch.resv_ram < base[1] + size[1])
		size[1] = gd->arch.resv_ram - base[1];
#endif

	fdt_fixup_memory_banks(blob, base, size, 2);

	fdt_fixup_icid(blob);

#ifdef CONFIG_FSL_ENETC
	fdt_fixup_enetc_mac(blob);
#endif

	return 0;
}
#endif

#ifdef CONFIG_FSL_QIXIS
int checkboard(void)
{
#ifdef CONFIG_TFABOOT
	enum boot_src src = get_boot_src();
#endif
	u8 sw;

	int clock;
	char *board;
	char buf[64] = {0};
	static const char *freq[6] = {"100.00", "125.00", "156.25",
					"161.13", "322.26", "100.00 SS"};

	cpu_name(buf);
	/* find the board details */
	sw = QIXIS_READ(id);

	switch (sw) {
	case 0x46:
		board = "QDS";
		break;
	case 0x47:
		board = "RDB";
		break;
	case 0x49:
		board = "HSSI";
		break;
	default:
		board = "unknown";
		break;
	}

	sw = QIXIS_READ(arch);
	printf("Board: %s-%s, Version: %c, boot from ",
	       buf, board, (sw & 0xf) + 'A' - 1);

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

#ifdef CONFIG_TFABOOT
	if (src == BOOT_SOURCE_SD_MMC) {
		puts("SD\n");
	} else if (src == BOOT_SOURCE_SD_MMC2) {
		puts("eMMC\n");
	} else {
#endif
#ifdef CONFIG_SD_BOOT
		puts("SD\n");
#elif defined(CONFIG_EMMC_BOOT)
		puts("eMMC\n");
#else
		switch (sw) {
		case 0:
		case 4:
			printf("NOR\n");
			break;
		case 1:
			printf("NAND\n");
			break;
		default:
			printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
			break;
		}
#endif
#ifdef CONFIG_TFABOOT
	}
#endif

	printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
	puts("SERDES1 Reference : ");

	sw = QIXIS_READ(brdcfg[2]);
#ifdef CONFIG_TARGET_LS1028ARDB
	clock = (sw >> 6) & 3;
#else
	clock = (sw >> 4) & 0xf;
#endif

	printf("Clock1 = %sMHz ", freq[clock]);
#ifdef CONFIG_TARGET_LS1028ARDB
	clock = (sw >> 4) & 3;
#else
	clock = sw & 0xf;
#endif
	printf("Clock2 = %sMHz\n", freq[clock]);

	return 0;
}
#endif
Commit	Line	Data
353f36d9 YT	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2019 NXP
	4	*/
	5
	6	#include <common.h>
691d719d	7	#include <init.h>
353f36d9 YT	8	#include <malloc.h>
	9	#include <errno.h>
	10	#include <fsl_ddr.h>
90526e9f	11	#include <net.h>
353f36d9 YT	12	#include <asm/io.h>
	13	#include <hwconfig.h>
	14	#include <fdt_support.h>
	15	#include <linux/libfdt.h>
f3998fdc	16	#include <env_internal.h>
353f36d9	17	#include <asm/arch-fsl-layerscape/soc.h>
b249fcba	18	#include <asm/arch-fsl-layerscape/fsl_icid.h>
353f36d9 YT	19	#include <i2c.h>
	20	#include <asm/arch/soc.h>
	21	#ifdef CONFIG_FSL_LS_PPA
	22	#include <asm/arch/ppa.h>
	23	#endif
	24	#include <fsl_immap.h>
	25	#include <netdev.h>
	26
	27	#include <fdtdec.h>
	28	#include <miiphy.h>
	29	#include "../common/qixis.h"
9c2aee1b	30	#include "../drivers/net/fsl_enetc.h"
353f36d9 YT	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
f278a217 YT	34	int config_board_mux(void)
f278a217 YT	35	{
7dfa44f7	36	#ifndef CONFIG_LPUART
f278a217 YT	37	#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
	38	u8 reg;
	39
	40	reg = QIXIS_READ(brdcfg[13]);
	41	/* Field\| Function
	42	* 7-6 \| Controls I2C3 routing (net CFG_MUX_I2C3):
	43	* I2C3 \| 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
	44	* 5-4 \| Controls I2C4 routing (net CFG_MUX_I2C4):
	45	* I2C4 \|11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
	46	*/
	47	reg &= ~(0xf0);
	48	reg \|= 0xb0;
	49	QIXIS_WRITE(brdcfg[13], reg);
	50
	51	reg = QIXIS_READ(brdcfg[15]);
	52	/* Field\| Function
	53	* 7 \| Controls the CAN1 transceiver (net CFG_CAN1_STBY):
	54	* CAN1 \| 0= CAN #1 transceiver enabled
	55	* 6 \| Controls the CAN2 transceiver (net CFG_CAN2_STBY):
	56	* CAN2 \| 0= CAN #2 transceiver enabled
	57	*/
	58	reg &= ~(0xc0);
	59	QIXIS_WRITE(brdcfg[15], reg);
	60	#endif
7dfa44f7 YT	61	#endif
7dfa44f7 YT	62
f278a217 YT	63	return 0;
	64	}
	65
7dfa44f7 YT	66	#ifdef CONFIG_LPUART
	67	u32 get_lpuart_clk(void)
	68	{
	69	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
	70	}
	71	#endif
	72
353f36d9 YT	73	int board_init(void)
	74	{
	75	#ifdef CONFIG_ENV_IS_NOWHERE
	76	gd->env_addr = (ulong)&default_environment[0];
	77	#endif
	78
72c3bfaa UA	79	#ifdef CONFIG_FSL_CAAM
	80	sec_init();
	81	#endif
	82
353f36d9 YT	83	#ifdef CONFIG_FSL_LS_PPA
	84	ppa_init();
	85	#endif
	86
	87	#ifndef CONFIG_SYS_EARLY_PCI_INIT
	88	pci_init();
	89	#endif
	90
	91	#if defined(CONFIG_TARGET_LS1028ARDB)
	92	u8 val = I2C_MUX_CH_DEFAULT;
	93
954cd788	94	#ifndef CONFIG_DM_I2C
353f36d9	95	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
954cd788 CH	96	#else
	97	struct udevice *dev;
	98
	99	if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
	100	dm_i2c_write(dev, 0x0b, &val, 1);
	101	#endif
f76d88b0	102	#endif
954cd788	103
f76d88b0 WH	104	#if defined(CONFIG_TARGET_LS1028ARDB)
	105	u8 reg;
	106
	107	reg = QIXIS_READ(brdcfg[4]);
	108	/*
	109	* Field \| Function
	110	* 3 \| DisplayPort Power Enable (net DP_PWR_EN):
	111	* DPPWR \| 0= DP_PWR is enabled.
	112	*/
	113	reg &= ~(DP_PWD_EN_DEFAULT_MASK);
	114	QIXIS_WRITE(brdcfg[4], reg);
353f36d9 YT	115	#endif
	116	return 0;
	117	}
	118
b75d8dc5	119	int board_eth_init(struct bd_info *bis)
353f36d9 YT	120	{
	121	return pci_eth_init(bis);
	122	}
	123
a2a14746 AM	124	#ifdef CONFIG_MISC_INIT_R
a2a14746 AM	125	int misc_init_r(void)
f278a217 YT	126	{
	127	config_board_mux();
	128
	129	return 0;
	130	}
	131	#endif
	132
353f36d9 YT	133	int board_early_init_f(void)
353f36d9 YT	134	{
7dfa44f7 YT	135	#ifdef CONFIG_LPUART
	136	u8 uart;
	137	#endif
	138
353f36d9 YT	139	#ifdef CONFIG_SYS_I2C_EARLY_INIT
	140	i2c_early_init_f();
	141	#endif
	142
	143	fsl_lsch3_early_init_f();
7dfa44f7 YT	144
	145	#ifdef CONFIG_LPUART
	146	/*
	147	* Field\| Function
	148	* --------------------------------------------------------------
	149	* 7-6 \| Controls I2C3 routing (net CFG_MUX_I2C3):
	150	* I2C3 \| 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
	151	* --------------------------------------------------------------
	152	* 5-4 \| Controls I2C4 routing (net CFG_MUX_I2C4):
	153	* I2C4 \|11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
	154	*/
	155	/* use lpuart0 as system console */
	156	uart = QIXIS_READ(brdcfg[13]);
	157	uart &= ~CFG_LPUART_MUX_MASK;
	158	uart \|= CFG_LPUART_EN;
	159	QIXIS_WRITE(brdcfg[13], uart);
	160	#endif
	161
353f36d9 YT	162	return 0;
	163	}
	164
	165	void detail_board_ddr_info(void)
	166	{
	167	puts("\nDDR ");
	168	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	169	print_ddr_info(0);
	170	}
	171
316fc6ff YZ	172	int esdhc_status_fixup(void blob, const char compat)
	173	{
	174	void __iomem dcfg_ccsr = (void __iomem )DCFG_BASE;
	175	char esdhc1_path[] = "/soc/mmc@2140000";
	176	char esdhc2_path[] = "/soc/mmc@2150000";
	177	char dspi1_path[] = "/soc/spi@2100000";
	178	char dspi2_path[] = "/soc/spi@2110000";
	179	u32 mux_sdhc1, mux_sdhc2;
	180	u32 io = 0;
	181
	182	/*
	183	* The PMUX IO-expander for mux select is used to control
	184	* the muxing of various onboard interfaces.
	185	*/
	186
	187	io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
	188	mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
	189
	190	/* Disable esdhc1/dspi1 if not selected. */
	191	if (mux_sdhc1 != 0)
	192	do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
	193	sizeof("disabled"), 1);
	194	if (mux_sdhc1 != 2)
	195	do_fixup_by_path(blob, dspi1_path, "status", "disabled",
	196	sizeof("disabled"), 1);
	197
	198	io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
	199	mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
	200
	201	/* Disable esdhc2/dspi2 if not selected. */
	202	if (mux_sdhc2 != 0)
	203	do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
	204	sizeof("disabled"), 1);
	205	if (mux_sdhc2 != 2)
	206	do_fixup_by_path(blob, dspi2_path, "status", "disabled",
	207	sizeof("disabled"), 1);
	208
	209	return 0;
	210	}
	211
353f36d9	212	#ifdef CONFIG_OF_BOARD_SETUP
b75d8dc5	213	int ft_board_setup(void blob, struct bd_info bd)
353f36d9 YT	214	{
	215	u64 base[CONFIG_NR_DRAM_BANKS];
	216	u64 size[CONFIG_NR_DRAM_BANKS];
	217
	218	ft_cpu_setup(blob, bd);
	219
	220	/* fixup DT for the two GPP DDR banks */
	221	base[0] = gd->bd->bi_dram[0].start;
	222	size[0] = gd->bd->bi_dram[0].size;
	223	base[1] = gd->bd->bi_dram[1].start;
	224	size[1] = gd->bd->bi_dram[1].size;
	225
	226	#ifdef CONFIG_RESV_RAM
	227	/* reduce size if reserved memory is within this bank */
	228	if (gd->arch.resv_ram >= base[0] &&
	229	gd->arch.resv_ram < base[0] + size[0])
	230	size[0] = gd->arch.resv_ram - base[0];
	231	else if (gd->arch.resv_ram >= base[1] &&
	232	gd->arch.resv_ram < base[1] + size[1])
	233	size[1] = gd->arch.resv_ram - base[1];
	234	#endif
	235
	236	fdt_fixup_memory_banks(blob, base, size, 2);
	237
b249fcba LT	238	fdt_fixup_icid(blob);
b249fcba LT	239
9c2aee1b AM	240	#ifdef CONFIG_FSL_ENETC
	241	fdt_fixup_enetc_mac(blob);
	242	#endif
	243
353f36d9 YT	244	return 0;
	245	}
	246	#endif
	247
	248	#ifdef CONFIG_FSL_QIXIS
	249	int checkboard(void)
	250	{
	251	#ifdef CONFIG_TFABOOT
	252	enum boot_src src = get_boot_src();
	253	#endif
	254	u8 sw;
	255
	256	int clock;
	257	char *board;
	258	char buf[64] = {0};
	259	static const char *freq[6] = {"100.00", "125.00", "156.25",
	260	"161.13", "322.26", "100.00 SS"};
	261
	262	cpu_name(buf);
	263	/* find the board details */
	264	sw = QIXIS_READ(id);
	265
	266	switch (sw) {
	267	case 0x46:
	268	board = "QDS";
	269	break;
	270	case 0x47:
	271	board = "RDB";
	272	break;
	273	case 0x49:
	274	board = "HSSI";
	275	break;
	276	default:
	277	board = "unknown";
	278	break;
	279	}
	280
	281	sw = QIXIS_READ(arch);
	282	printf("Board: %s-%s, Version: %c, boot from ",
	283	buf, board, (sw & 0xf) + 'A' - 1);
	284
	285	sw = QIXIS_READ(brdcfg[0]);
	286	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	287
	288	#ifdef CONFIG_TFABOOT
	289	if (src == BOOT_SOURCE_SD_MMC) {
	290	puts("SD\n");
	291	} else if (src == BOOT_SOURCE_SD_MMC2) {
	292	puts("eMMC\n");
	293	} else {
	294	#endif
	295	#ifdef CONFIG_SD_BOOT
	296	puts("SD\n");
	297	#elif defined(CONFIG_EMMC_BOOT)
	298	puts("eMMC\n");
	299	#else
	300	switch (sw) {
	301	case 0:
	302	case 4:
	303	printf("NOR\n");
	304	break;
	305	case 1:
	306	printf("NAND\n");
	307	break;
308	default:
309	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
310	break;
311	}
312	#endif
313	#ifdef CONFIG_TFABOOT
314	}
315	#endif
316
317	printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
318	puts("SERDES1 Reference : ");
319
320	sw = QIXIS_READ(brdcfg[2]);
321	#ifdef CONFIG_TARGET_LS1028ARDB
322	clock = (sw >> 6) & 3;
323	#else
324	clock = (sw >> 4) & 0xf;
325	#endif
326
327	printf("Clock1 = %sMHz ", freq[clock]);
328	#ifdef CONFIG_TARGET_LS1028ARDB
329	clock = (sw >> 4) & 3;
330	#else
331	clock = sw & 0xf;
332	#endif
333	printf("Clock2 = %sMHz\n", freq[clock]);
334
335	return 0;
336	}
337	#endif