Commit | Line | Data |
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1cb8e980 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
f3108304 | 6 | * (C) Copyright 2002, 2010 |
1cb8e980 WD |
7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
1cb8e980 WD |
10 | */ |
11 | ||
12 | #include <common.h> | |
b1c0eaac | 13 | #include <netdev.h> |
1cb8e980 | 14 | #include <i2c.h> |
f3108304 DMEA |
15 | #include <asm/io.h> |
16 | #include <asm/arch/s3c24x0_cpu.h> | |
1cb8e980 WD |
17 | |
18 | #include "vcma9.h" | |
19 | #include "../common/common_util.h" | |
20 | ||
d87080b7 | 21 | DECLARE_GLOBAL_DATA_PTR; |
1cb8e980 | 22 | |
1cb8e980 WD |
23 | /* |
24 | * Miscellaneous platform dependent initialisations | |
25 | */ | |
26 | ||
f3108304 | 27 | int board_early_init_f(void) |
1cb8e980 | 28 | { |
eb0ae7f5 | 29 | struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); |
1cb8e980 | 30 | |
1cb8e980 | 31 | /* set up the I/O ports */ |
f3108304 DMEA |
32 | writel(0x007FFFFF, &gpio->gpacon); |
33 | writel(0x002AAAAA, &gpio->gpbcon); | |
34 | writel(0x000002BF, &gpio->gpbup); | |
35 | writel(0xAAAAAAAA, &gpio->gpccon); | |
36 | writel(0x0000FFFF, &gpio->gpcup); | |
37 | writel(0xAAAAAAAA, &gpio->gpdcon); | |
38 | writel(0x0000FFFF, &gpio->gpdup); | |
39 | writel(0xAAAAAAAA, &gpio->gpecon); | |
40 | writel(0x000037F7, &gpio->gpeup); | |
41 | writel(0x00000000, &gpio->gpfcon); | |
42 | writel(0x00000000, &gpio->gpfup); | |
43 | writel(0xFFEAFF5A, &gpio->gpgcon); | |
44 | writel(0x0000F0DC, &gpio->gpgup); | |
45 | writel(0x0028AAAA, &gpio->gphcon); | |
46 | writel(0x00000656, &gpio->gphup); | |
47 | ||
48 | /* setup correct IRQ modes for NIC (rising edge mode) */ | |
49 | writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); | |
50 | ||
51 | /* select USB port 2 to be host or device (setup as host for now) */ | |
52 | writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); | |
1cb8e980 | 53 | |
f3108304 DMEA |
54 | return 0; |
55 | } | |
56 | ||
57 | int board_init(void) | |
58 | { | |
1cb8e980 WD |
59 | /* adress of boot parameters */ |
60 | gd->bd->bi_boot_params = 0x30000100; | |
61 | ||
62 | icache_enable(); | |
63 | dcache_enable(); | |
64 | ||
65 | return 0; | |
66 | } | |
67 | ||
1cb8e980 WD |
68 | /* |
69 | * Get some Board/PLD Info | |
70 | */ | |
71 | ||
f3108304 | 72 | static u8 get_pld_reg(enum vcma9_pld_regs reg) |
531716e1 | 73 | { |
f3108304 | 74 | return readb(VCMA9_PLD_BASE + reg); |
531716e1 WD |
75 | } |
76 | ||
f3108304 | 77 | static u8 get_pld_version(void) |
1cb8e980 | 78 | { |
f3108304 | 79 | return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; |
1cb8e980 WD |
80 | } |
81 | ||
f3108304 | 82 | static u8 get_pld_revision(void) |
1cb8e980 | 83 | { |
f3108304 | 84 | return get_pld_reg(VCMA9_PLD_ID) & 0x0F; |
1cb8e980 WD |
85 | } |
86 | ||
f3108304 | 87 | static uchar get_board_pcb(void) |
1cb8e980 | 88 | { |
f3108304 | 89 | return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; |
1cb8e980 WD |
90 | } |
91 | ||
f3108304 | 92 | static u8 get_nr_chips(void) |
1cb8e980 | 93 | { |
f3108304 | 94 | switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { |
531716e1 WD |
95 | case 0: return 4; |
96 | case 1: return 1; | |
97 | case 2: return 2; | |
98 | default: return 0; | |
99 | } | |
100 | } | |
101 | ||
f3108304 | 102 | static ulong get_chip_size(void) |
531716e1 | 103 | { |
f3108304 | 104 | switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { |
531716e1 WD |
105 | case 0: return 16 * (1024*1024); |
106 | case 1: return 32 * (1024*1024); | |
107 | case 2: return 8 * (1024*1024); | |
108 | case 3: return 8 * (1024*1024); | |
109 | default: return 0; | |
42d1f039 | 110 | } |
531716e1 | 111 | } |
f3108304 DMEA |
112 | |
113 | static const char *get_chip_geom(void) | |
531716e1 | 114 | { |
f3108304 | 115 | switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { |
531716e1 WD |
116 | case 0: return "4Mx8x4"; |
117 | case 1: return "8Mx8x4"; | |
118 | case 2: return "2Mx8x4"; | |
119 | case 3: return "4Mx8x2"; | |
120 | default: return "unknown"; | |
121 | } | |
122 | } | |
123 | ||
f3108304 | 124 | static void vcma9_show_info(char *board_name, char *serial) |
531716e1 WD |
125 | { |
126 | printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", | |
f3108304 DMEA |
127 | board_name, serial, |
128 | get_board_pcb(), get_pld_version(), get_pld_revision()); | |
129 | printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); | |
531716e1 WD |
130 | } |
131 | ||
132 | int dram_init(void) | |
133 | { | |
f3108304 DMEA |
134 | /* dram_init must store complete ramsize in gd->ram_size */ |
135 | gd->ram_size = get_chip_size() * get_nr_chips(); | |
531716e1 WD |
136 | return 0; |
137 | } | |
138 | ||
1cb8e980 WD |
139 | /* |
140 | * Check Board Identity: | |
141 | */ | |
142 | ||
143 | int checkboard(void) | |
144 | { | |
fc19e36f | 145 | char s[50]; |
1cb8e980 WD |
146 | int i; |
147 | backup_t *b = (backup_t *) s; | |
148 | ||
cdb74977 | 149 | i = getenv_f("serial#", s, 32); |
1cb8e980 WD |
150 | if ((i < 0) || strncmp (s, "VCMA9", 5)) { |
151 | get_backup_values (b); | |
152 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
153 | puts ("### No HW ID - assuming VCMA9"); | |
154 | } else { | |
155 | b->serial_name[5] = 0; | |
f3108304 | 156 | vcma9_show_info(b->serial_name, &b->serial_name[6]); |
1cb8e980 WD |
157 | } |
158 | } else { | |
159 | s[5] = 0; | |
f3108304 | 160 | vcma9_show_info(s, &s[6]); |
1cb8e980 | 161 | } |
1cb8e980 | 162 | |
1cb8e980 WD |
163 | return 0; |
164 | } | |
165 | ||
f3108304 | 166 | int board_late_init(void) |
1cb8e980 | 167 | { |
f3108304 DMEA |
168 | /* |
169 | * check if environment is healthy, otherwise restore values | |
170 | * from shadow copy | |
171 | */ | |
172 | check_env(); | |
1cb8e980 WD |
173 | return 0; |
174 | } | |
1cb8e980 | 175 | |
f3108304 | 176 | void vcma9_print_info(void) |
42d1f039 | 177 | { |
f3108304 | 178 | char *s = getenv("serial#"); |
42d1f039 | 179 | |
f3108304 | 180 | if (!s) { |
531716e1 | 181 | puts ("### No HW ID - assuming VCMA9"); |
531716e1 WD |
182 | } else { |
183 | s[5] = 0; | |
f3108304 | 184 | vcma9_show_info(s, &s[6]); |
531716e1 | 185 | } |
1cb8e980 | 186 | } |
b1c0eaac BW |
187 | |
188 | #ifdef CONFIG_CMD_NET | |
189 | int board_eth_init(bd_t *bis) | |
190 | { | |
191 | int rc = 0; | |
192 | #ifdef CONFIG_CS8900 | |
193 | rc = cs8900_initialize(0, CONFIG_CS8900_BASE); | |
194 | #endif | |
195 | return rc; | |
196 | } | |
197 | #endif | |
6d754843 DMEA |
198 | |
199 | /* | |
200 | * Hardcoded flash setup: | |
201 | * Flash 0 is a non-CFI AMD AM29F400BB flash. | |
202 | */ | |
203 | ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) | |
204 | { | |
205 | info->portwidth = FLASH_CFI_16BIT; | |
206 | info->chipwidth = FLASH_CFI_BY16; | |
207 | info->interface = FLASH_CFI_X16; | |
208 | return 1; | |
209 | } |