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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
c609719b
WD
2/*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <[email protected]>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, [email protected].
8 * Wolfgang Grandegger, DENX Software Engineering, [email protected].
c609719b
WD
9 */
10
11/*
12 * PCI routines
13 */
14
15#include <common.h>
0098e179 16#include <bootretry.h>
18d66533 17#include <cli.h>
c609719b 18#include <command.h>
24b852a7 19#include <console.h>
cab24b34 20#include <dm.h>
691d719d 21#include <init.h>
c609719b
WD
22#include <asm/processor.h>
23#include <asm/io.h>
c609719b
WD
24#include <pci.h>
25
07a58870
SG
26struct pci_reg_info {
27 const char *name;
28 enum pci_size_t size;
29 u8 offset;
30};
31
72ef5b60 32static int pci_byte_size(enum pci_size_t size)
07a58870
SG
33{
34 switch (size) {
35 case PCI_SIZE_8:
72ef5b60 36 return 1;
07a58870 37 case PCI_SIZE_16:
72ef5b60 38 return 2;
07a58870
SG
39 case PCI_SIZE_32:
40 default:
72ef5b60 41 return 4;
07a58870
SG
42 }
43}
44
72ef5b60
SG
45static int pci_field_width(enum pci_size_t size)
46{
47 return pci_byte_size(size) * 2;
48}
49
cab24b34
SG
50static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
51{
52 for (; regs->name; regs++) {
53 unsigned long val;
54
55 dm_pci_read_config(dev, regs->offset, &val, regs->size);
56 printf(" %s =%*s%#.*lx\n", regs->name,
57 (int)(28 - strlen(regs->name)), "",
58 pci_field_width(regs->size), val);
59 }
60}
07a58870 61
f5164f6b 62static int pci_bar_show(struct udevice *dev)
e5f96a87
YY
63{
64 u8 header_type;
65 int bar_cnt, bar_id, mem_type;
66 bool is_64, is_io;
67 u32 base_low, base_high;
68 u32 size_low, size_high;
69 u64 base, size;
70 u32 reg_addr;
71 int prefetchable;
72
73 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
e6335d3e 74 header_type &= 0x7f;
e5f96a87
YY
75
76 if (header_type == PCI_HEADER_TYPE_CARDBUS) {
77 printf("CardBus doesn't support BARs\n");
78 return -ENOSYS;
e6335d3e
T
79 } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
80 header_type != PCI_HEADER_TYPE_BRIDGE) {
81 printf("unknown header type\n");
82 return -ENOSYS;
e5f96a87
YY
83 }
84
85 bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
86
87 printf("ID Base Size Width Type\n");
88 printf("----------------------------------------------------------\n");
89
90 bar_id = 0;
91 reg_addr = PCI_BASE_ADDRESS_0;
92 while (bar_cnt) {
93 dm_pci_read_config32(dev, reg_addr, &base_low);
94 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
95 dm_pci_read_config32(dev, reg_addr, &size_low);
96 dm_pci_write_config32(dev, reg_addr, base_low);
97 reg_addr += 4;
98
99 base = base_low & ~0xf;
100 size = size_low & ~0xf;
101 base_high = 0x0;
102 size_high = 0xffffffff;
103 is_64 = 0;
104 prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
105 is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
106 mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
107
108 if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
109 dm_pci_read_config32(dev, reg_addr, &base_high);
110 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
111 dm_pci_read_config32(dev, reg_addr, &size_high);
112 dm_pci_write_config32(dev, reg_addr, base_high);
113 bar_cnt--;
114 reg_addr += 4;
115 is_64 = 1;
116 }
117
118 base = base | ((u64)base_high << 32);
119 size = size | ((u64)size_high << 32);
120
121 if ((!is_64 && size_low) || (is_64 && size)) {
122 size = ~size + 1;
4ebeb4c5 123 printf(" %d %#018llx %#018llx %d %s %s\n",
84d7f916
SG
124 bar_id, (unsigned long long)base,
125 (unsigned long long)size, is_64 ? 64 : 32,
e5f96a87
YY
126 is_io ? "I/O" : "MEM",
127 prefetchable ? "Prefetchable" : "");
128 }
129
130 bar_id++;
131 bar_cnt--;
132 }
133
134 return 0;
135}
e5f96a87 136
07a58870
SG
137static struct pci_reg_info regs_start[] = {
138 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
139 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
140 { "command register ID", PCI_SIZE_16, PCI_COMMAND },
141 { "status register", PCI_SIZE_16, PCI_STATUS },
142 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
143 {},
144};
145
146static struct pci_reg_info regs_rest[] = {
147 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
148 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
149 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
150 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
151 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
152 { "BIST", PCI_SIZE_8, PCI_BIST },
153 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
154 {},
155};
156
157static struct pci_reg_info regs_normal[] = {
158 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
159 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
160 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
161 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
162 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
163 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
164 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
165 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
166 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
167 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
168 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
169 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
170 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
171 {},
172};
173
174static struct pci_reg_info regs_bridge[] = {
175 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
176 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
177 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
178 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
179 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
180 { "IO base", PCI_SIZE_8, PCI_IO_BASE },
181 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
182 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
183 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
184 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
185 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
186 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
187 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
188 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
189 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
190 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
191 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
192 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
193 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
194 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
195 {},
196};
197
198static struct pci_reg_info regs_cardbus[] = {
199 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
200 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
201 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
202 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
203 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
204 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
205 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
206 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
207 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
208 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
209 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
210 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
211 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
212 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
213 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
214 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
215 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
216 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
217 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
218 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
219 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
220 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
221 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
222 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
223 {},
224};
225
c2be0700
SG
226/**
227 * pci_header_show() - Show the header of the specified PCI device.
c609719b 228 *
c2be0700 229 * @dev: Bus+Device+Function number
c609719b 230 */
a95f8ee9 231static void pci_header_show(struct udevice *dev)
c609719b 232{
cab24b34
SG
233 unsigned long class, header_type;
234
235 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
236 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
07a58870 237 pci_show_regs(dev, regs_start);
cab24b34 238 printf(" class code = 0x%.2x (%s)\n", (int)class,
07a58870
SG
239 pci_class_str(class));
240 pci_show_regs(dev, regs_rest);
c609719b 241
43dad07c 242 switch (header_type & 0x7f) {
7c7a23bd 243 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
07a58870 244 pci_show_regs(dev, regs_normal);
7c7a23bd 245 break;
7c7a23bd 246 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
07a58870 247 pci_show_regs(dev, regs_bridge);
7c7a23bd 248 break;
7c7a23bd 249 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
07a58870 250 pci_show_regs(dev, regs_cardbus);
7c7a23bd 251 break;
8bde7f77 252
7c7a23bd
WD
253 default:
254 printf("unknown header\n");
8bde7f77 255 break;
c609719b 256 }
c609719b
WD
257}
258
1a4942f1 259static void pciinfo_header(bool short_listing)
c4f32bb2 260{
c4f32bb2
SG
261 if (short_listing) {
262 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
263 printf("_____________________________________________________________\n");
264 }
265}
266
cab24b34
SG
267/**
268 * pci_header_show_brief() - Show the short-form PCI device header
269 *
270 * Reads and prints the header of the specified PCI device in short form.
271 *
272 * @dev: PCI device to show
273 */
274static void pci_header_show_brief(struct udevice *dev)
275{
276 ulong vendor, device;
277 ulong class, subclass;
278
279 dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
280 dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
281 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
282 dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
283
284 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
285 vendor, device,
286 pci_class_str(class), subclass);
287}
288
1a4942f1 289static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
cab24b34
SG
290{
291 struct udevice *dev;
292
1a4942f1
T
293 if (!multi)
294 printf("Scanning PCI devices on bus %d\n", dev_seq(bus));
295
296 if (!multi || dev_seq(bus) == 0)
297 pciinfo_header(short_listing);
cab24b34
SG
298
299 for (device_find_first_child(bus, &dev);
300 dev;
301 device_find_next_child(&dev)) {
8a8d24bd 302 struct pci_child_plat *pplat;
cab24b34 303
caa4daa2 304 pplat = dev_get_parent_plat(dev);
cab24b34 305 if (short_listing) {
8b85dfc6 306 printf("%02x.%02x.%02x ", dev_seq(bus),
cab24b34
SG
307 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
308 pci_header_show_brief(dev);
309 } else {
8b85dfc6
SG
310 printf("\nFound PCI device %02x.%02x.%02x:\n",
311 dev_seq(bus),
cab24b34
SG
312 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
313 pci_header_show(dev);
314 }
315 }
316}
317
c2be0700
SG
318/**
319 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
320 *
321 * @name: Device string in the form "bus.device.function" where each is in hex
185f812c 322 * Return: encoded pci_dev_t or -1 if the string was invalid
c609719b 323 */
c2be0700 324static pci_dev_t get_pci_dev(char *name)
c609719b
WD
325{
326 char cnum[12];
327 int len, i, iold, n;
328 int bdfs[3] = {0,0,0};
329
330 len = strlen(name);
331 if (len > 8)
332 return -1;
333 for (i = 0, iold = 0, n = 0; i < len; i++) {
334 if (name[i] == '.') {
335 memcpy(cnum, &name[iold], i - iold);
336 cnum[i - iold] = '\0';
7e5f460e 337 bdfs[n++] = hextoul(cnum, NULL);
c609719b
WD
338 iold = i + 1;
339 }
340 }
341 strcpy(cnum, &name[iold]);
342 if (n == 0)
343 n = 1;
7e5f460e 344 bdfs[n] = hextoul(cnum, NULL);
c2be0700 345
c609719b
WD
346 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
347}
348
cab24b34
SG
349static int pci_cfg_display(struct udevice *dev, ulong addr,
350 enum pci_size_t size, ulong length)
c609719b
WD
351{
352#define DISP_LINE_LEN 16
353 ulong i, nbytes, linebytes;
72ef5b60 354 int byte_size;
c609719b
WD
355 int rc = 0;
356
72ef5b60 357 byte_size = pci_byte_size(size);
c609719b 358 if (length == 0)
72ef5b60 359 length = 0x40 / byte_size; /* Standard PCI config space */
c609719b
WD
360
361 /* Print the lines.
362 * once, and all accesses are with the specified bus width.
363 */
72ef5b60 364 nbytes = length * byte_size;
c609719b 365 do {
c609719b 366 printf("%08lx:", addr);
72ef5b60
SG
367 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
368 for (i = 0; i < linebytes; i += byte_size) {
369 unsigned long val;
370
cab24b34 371 dm_pci_read_config(dev, addr, &val, size);
72ef5b60
SG
372 printf(" %0*lx", pci_field_width(size), val);
373 addr += byte_size;
c609719b
WD
374 }
375 printf("\n");
376 nbytes -= linebytes;
377 if (ctrlc()) {
378 rc = 1;
379 break;
380 }
381 } while (nbytes > 0);
382
383 return (rc);
384}
385
cab24b34 386static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
72ef5b60 387 ulong value, int incrflag)
c609719b
WD
388{
389 ulong i;
390 int nbytes;
72ef5b60 391 ulong val;
c609719b
WD
392
393 /* Print the address, followed by value. Then accept input for
394 * the next value. A non-converted value exits.
395 */
396 do {
397 printf("%08lx:", addr);
cab24b34 398 dm_pci_read_config(dev, addr, &val, size);
72ef5b60 399 printf(" %0*lx", pci_field_width(size), val);
c609719b 400
e1bf824d 401 nbytes = cli_readline(" ? ");
c609719b
WD
402 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
403 /* <CR> pressed as only input, don't modify current
404 * location and move to next. "-" pressed will go back.
405 */
406 if (incrflag)
407 addr += nbytes ? -size : size;
408 nbytes = 1;
b26440f1
SG
409 /* good enough to not time out */
410 bootretry_reset_cmd_timeout();
c609719b
WD
411 }
412#ifdef CONFIG_BOOT_RETRY_TIME
413 else if (nbytes == -2) {
414 break; /* timed out, exit the command */
415 }
416#endif
417 else {
418 char *endp;
7e5f460e 419 i = hextoul(console_buffer, &endp);
c609719b
WD
420 nbytes = endp - console_buffer;
421 if (nbytes) {
c609719b
WD
422 /* good enough to not time out
423 */
b26440f1 424 bootretry_reset_cmd_timeout();
cab24b34 425 dm_pci_write_config(dev, addr, i, size);
c609719b
WD
426 if (incrflag)
427 addr += size;
428 }
429 }
430 } while (nbytes);
431
432 return 0;
433}
434
b997a73e
SG
435static const struct pci_flag_info {
436 uint flag;
437 const char *name;
438} pci_flag_info[] = {
439 { PCI_REGION_IO, "io" },
440 { PCI_REGION_PREFETCH, "prefetch" },
441 { PCI_REGION_SYS_MEMORY, "sysmem" },
442 { PCI_REGION_RO, "readonly" },
443 { PCI_REGION_IO, "io" },
444};
445
446static void pci_show_regions(struct udevice *bus)
447{
39320935 448 struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus));
b997a73e
SG
449 const struct pci_region *reg;
450 int i, j;
451
452 if (!hose) {
453 printf("Bus '%s' is not a PCI controller\n", bus->name);
454 return;
455 }
456
39320935 457 printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
4ebeb4c5 458 printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
b997a73e
SG
459 "Flags");
460 for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
4ebeb4c5 461 printf("%d %#018llx %#018llx %#018llx ", i,
b997a73e
SG
462 (unsigned long long)reg->bus_start,
463 (unsigned long long)reg->phys_start,
464 (unsigned long long)reg->size);
465 if (!(reg->flags & PCI_REGION_TYPE))
466 printf("mem ");
467 for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
468 if (reg->flags & pci_flag_info[j].flag)
469 printf("%s ", pci_flag_info[j].name);
470 }
471 printf("\n");
472 }
473}
b997a73e 474
c609719b
WD
475/* PCI Configuration Space access commands
476 *
477 * Syntax:
478 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
479 * pci next[.b, .w, .l] bus.device.function [addr]
480 * pci modify[.b, .w, .l] bus.device.function [addr]
481 * pci write[.b, .w, .l] bus.device.function addr value
482 */
09140113 483static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
c609719b 484{
72ef5b60
SG
485 ulong addr = 0, value = 0, cmd_size = 0;
486 enum pci_size_t size = PCI_SIZE_32;
cab24b34 487 struct udevice *dev, *bus;
1a4942f1 488 int busnum = -1;
c609719b
WD
489 pci_dev_t bdf = 0;
490 char cmd = 's';
bfa4191e 491 int ret = 0;
1a4942f1 492 char *endp;
c609719b
WD
493
494 if (argc > 1)
495 cmd = argv[1][0];
496
497 switch (cmd) {
498 case 'd': /* display */
499 case 'n': /* next */
500 case 'm': /* modify */
501 case 'w': /* write */
502 /* Check for a size specification. */
72ef5b60
SG
503 cmd_size = cmd_get_data_size(argv[1], 4);
504 size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
c609719b 505 if (argc > 3)
7e5f460e 506 addr = hextoul(argv[3], NULL);
c609719b 507 if (argc > 4)
7e5f460e 508 value = hextoul(argv[4], NULL);
c609719b 509 case 'h': /* header */
e5f96a87 510 case 'b': /* bars */
c609719b
WD
511 if (argc < 3)
512 goto usage;
513 if ((bdf = get_pci_dev(argv[2])) == -1)
514 return 1;
515 break;
96d61603 516 case 'e':
e578b92c
SW
517 pci_init();
518 return 0;
b997a73e 519 case 'r': /* no break */
c609719b
WD
520 default: /* scan bus */
521 value = 1; /* short listing */
c609719b 522 if (argc > 1) {
b997a73e 523 if (cmd != 'r' && argv[argc-1][0] == 'l') {
c609719b
WD
524 value = 0;
525 argc--;
526 }
39320935 527 if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] != 's')) {
1a4942f1
T
528 if (argv[argc - 1][0] != '*') {
529 busnum = hextoul(argv[argc - 1], &endp);
530 if (*endp)
531 goto usage;
532 }
6850a5a8 533 argc--;
39320935 534 }
6850a5a8
T
535 if (cmd == 'r' && argc > 2)
536 goto usage;
537 else if (cmd != 'r' && (argc > 2 || (argc == 2 && argv[1][0] != 's')))
538 goto usage;
c609719b 539 }
1a4942f1
T
540 if (busnum == -1) {
541 if (cmd != 'r') {
542 for (busnum = 0;
543 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
544 busnum++)
545 pciinfo(bus, value, true);
546 } else {
547 for (busnum = 0;
548 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
549 busnum++) {
550 /* Regions are controller specific so skip non-root buses */
551 if (device_is_on_pci_bus(bus))
552 continue;
553 pci_show_regions(bus);
554 }
555 }
556 return 0;
557 }
cab24b34
SG
558 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
559 if (ret) {
560 printf("No such bus\n");
561 return CMD_RET_FAILURE;
562 }
b997a73e
SG
563 if (cmd == 'r')
564 pci_show_regions(bus);
565 else
1a4942f1 566 pciinfo(bus, value, false);
c609719b
WD
567 return 0;
568 }
569
f3f1faef 570 ret = dm_pci_bus_find_bdf(bdf, &dev);
cab24b34
SG
571 if (ret) {
572 printf("No such device\n");
573 return CMD_RET_FAILURE;
574 }
32ec5b34 575
c609719b
WD
576 switch (argv[1][0]) {
577 case 'h': /* header */
32ec5b34 578 pci_header_show(dev);
bfa4191e 579 break;
c609719b 580 case 'd': /* display */
32ec5b34 581 return pci_cfg_display(dev, addr, size, value);
c609719b
WD
582 case 'n': /* next */
583 if (argc < 4)
584 goto usage;
32ec5b34 585 ret = pci_cfg_modify(dev, addr, size, value, 0);
bfa4191e 586 break;
c609719b
WD
587 case 'm': /* modify */
588 if (argc < 4)
589 goto usage;
32ec5b34 590 ret = pci_cfg_modify(dev, addr, size, value, 1);
bfa4191e 591 break;
c609719b
WD
592 case 'w': /* write */
593 if (argc < 5)
594 goto usage;
cab24b34 595 ret = dm_pci_write_config(dev, addr, value, size);
bfa4191e 596 break;
e5f96a87
YY
597 case 'b': /* bars */
598 return pci_bar_show(dev);
bfa4191e
SG
599 default:
600 ret = CMD_RET_USAGE;
601 break;
c609719b
WD
602 }
603
bfa4191e 604 return ret;
c609719b 605 usage:
4c12eeb8 606 return CMD_RET_USAGE;
c609719b
WD
607}
608
8bde7f77
WD
609/***************************************************/
610
088f1b19
KP
611#ifdef CONFIG_SYS_LONGHELP
612static char pci_help_text[] =
1a4942f1 613 "[bus|*] [long]\n"
8bde7f77 614 " - short or long list of PCI devices on bus 'bus'\n"
96d61603 615 "pci enum\n"
e578b92c 616 " - Enumerate PCI buses\n"
8bde7f77
WD
617 "pci header b.d.f\n"
618 " - show header of PCI device 'bus.device.function'\n"
e5f96a87
YY
619 "pci bar b.d.f\n"
620 " - show BARs base and size for device b.d.f'\n"
1a4942f1 621 "pci regions [bus|*]\n"
b997a73e 622 " - show PCI regions\n"
8bde7f77
WD
623 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
624 " - display PCI configuration space (CFG)\n"
625 "pci next[.b, .w, .l] b.d.f address\n"
626 " - modify, read and keep CFG address\n"
627 "pci modify[.b, .w, .l] b.d.f address\n"
628 " - modify, auto increment CFG address\n"
629 "pci write[.b, .w, .l] b.d.f address value\n"
088f1b19
KP
630 " - write to CFG address";
631#endif
632
633U_BOOT_CMD(
634 pci, 5, 1, do_pci,
635 "list and access PCI Configuration Space", pci_help_text
8bde7f77 636);
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