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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
293eb33f | 2 | /* |
d9ae52c8 | 3 | * (C) Copyright 2013 - 2015 Xilinx, Inc. |
293eb33f MS |
4 | * |
5 | * Xilinx Zynq SD Host Controller Interface | |
293eb33f MS |
6 | */ |
7 | ||
e0f4de1a | 8 | #include <clk.h> |
293eb33f | 9 | #include <common.h> |
d9ae52c8 | 10 | #include <dm.h> |
345d3c0f | 11 | #include <fdtdec.h> |
d1f4e39d | 12 | #include "mmc_private.h" |
f7ae49fc | 13 | #include <log.h> |
336d4615 | 14 | #include <dm/device_compat.h> |
61b29b82 | 15 | #include <linux/err.h> |
b08c8c48 | 16 | #include <linux/libfdt.h> |
293eb33f MS |
17 | #include <malloc.h> |
18 | #include <sdhci.h> | |
d1f4e39d | 19 | #include <zynqmp_tap_delay.h> |
293eb33f | 20 | |
61e745d1 SH |
21 | DECLARE_GLOBAL_DATA_PTR; |
22 | ||
329a449f SG |
23 | struct arasan_sdhci_plat { |
24 | struct mmc_config cfg; | |
25 | struct mmc mmc; | |
26 | }; | |
27 | ||
d1f4e39d SDPP |
28 | struct arasan_sdhci_priv { |
29 | struct sdhci_host *host; | |
30 | u8 deviceid; | |
31 | u8 bank; | |
d1f4e39d SDPP |
32 | }; |
33 | ||
34 | #if defined(CONFIG_ARCH_ZYNQMP) | |
84333708 SDPP |
35 | #define MMC_HS200_BUS_SPEED 5 |
36 | ||
d1f4e39d | 37 | static const u8 mode2timing[] = { |
84333708 | 38 | [MMC_LEGACY] = UHS_SDR12_BUS_SPEED, |
84333708 SDPP |
39 | [MMC_HS] = HIGH_SPEED_BUS_SPEED, |
40 | [SD_HS] = HIGH_SPEED_BUS_SPEED, | |
41 | [MMC_HS_52] = HIGH_SPEED_BUS_SPEED, | |
42 | [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED, | |
43 | [UHS_SDR12] = UHS_SDR12_BUS_SPEED, | |
44 | [UHS_SDR25] = UHS_SDR25_BUS_SPEED, | |
45 | [UHS_SDR50] = UHS_SDR50_BUS_SPEED, | |
46 | [UHS_DDR50] = UHS_DDR50_BUS_SPEED, | |
47 | [UHS_SDR104] = UHS_SDR104_BUS_SPEED, | |
48 | [MMC_HS_200] = MMC_HS200_BUS_SPEED, | |
d1f4e39d SDPP |
49 | }; |
50 | ||
d1f4e39d SDPP |
51 | #define SDHCI_TUNING_LOOP_COUNT 40 |
52 | ||
53 | static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid) | |
54 | { | |
55 | u16 clk; | |
56 | unsigned long timeout; | |
57 | ||
58 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
59 | clk &= ~(SDHCI_CLOCK_CARD_EN); | |
60 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
61 | ||
62 | /* Issue DLL Reset */ | |
63 | zynqmp_dll_reset(deviceid); | |
64 | ||
65 | /* Wait max 20 ms */ | |
66 | timeout = 100; | |
67 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
68 | & SDHCI_CLOCK_INT_STABLE)) { | |
69 | if (timeout == 0) { | |
70 | dev_err(mmc_dev(host->mmc), | |
71 | ": Internal clock never stabilised.\n"); | |
72 | return; | |
73 | } | |
74 | timeout--; | |
75 | udelay(1000); | |
76 | } | |
77 | ||
78 | clk |= SDHCI_CLOCK_CARD_EN; | |
79 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
80 | } | |
81 | ||
82 | static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) | |
83 | { | |
84 | struct mmc_cmd cmd; | |
85 | struct mmc_data data; | |
86 | u32 ctrl; | |
87 | struct sdhci_host *host; | |
88 | struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); | |
b6911780 | 89 | char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; |
d1f4e39d SDPP |
90 | u8 deviceid; |
91 | ||
92 | debug("%s\n", __func__); | |
93 | ||
94 | host = priv->host; | |
95 | deviceid = priv->deviceid; | |
96 | ||
d1c0a220 | 97 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
d1f4e39d | 98 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
d1c0a220 | 99 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
d1f4e39d SDPP |
100 | |
101 | mdelay(1); | |
102 | ||
103 | arasan_zynqmp_dll_reset(host, deviceid); | |
104 | ||
105 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); | |
106 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); | |
107 | ||
108 | do { | |
109 | cmd.cmdidx = opcode; | |
110 | cmd.resp_type = MMC_RSP_R1; | |
111 | cmd.cmdarg = 0; | |
112 | ||
113 | data.blocksize = 64; | |
114 | data.blocks = 1; | |
115 | data.flags = MMC_DATA_READ; | |
116 | ||
117 | if (tuning_loop_counter-- == 0) | |
118 | break; | |
119 | ||
120 | if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 && | |
121 | mmc->bus_width == 8) | |
122 | data.blocksize = 128; | |
123 | ||
124 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
125 | data.blocksize), | |
126 | SDHCI_BLOCK_SIZE); | |
127 | sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT); | |
128 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); | |
129 | ||
130 | mmc_send_cmd(mmc, &cmd, NULL); | |
d1c0a220 | 131 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
d1f4e39d SDPP |
132 | |
133 | if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK) | |
134 | udelay(1); | |
135 | ||
136 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); | |
137 | ||
138 | if (tuning_loop_counter < 0) { | |
139 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
d1c0a220 | 140 | sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2); |
d1f4e39d SDPP |
141 | } |
142 | ||
143 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | |
144 | printf("%s:Tuning failed\n", __func__); | |
145 | return -1; | |
146 | } | |
147 | ||
148 | udelay(1); | |
149 | arasan_zynqmp_dll_reset(host, deviceid); | |
150 | ||
151 | /* Enable only interrupts served by the SD controller */ | |
152 | sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, | |
153 | SDHCI_INT_ENABLE); | |
154 | /* Mask all sdhci interrupt sources */ | |
155 | sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static void arasan_sdhci_set_tapdelay(struct sdhci_host *host) | |
161 | { | |
162 | struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); | |
163 | struct mmc *mmc = (struct mmc *)host->mmc; | |
164 | u8 uhsmode; | |
165 | ||
d1f4e39d SDPP |
166 | uhsmode = mode2timing[mmc->selected_mode]; |
167 | ||
168 | if (uhsmode >= UHS_SDR25_BUS_SPEED) | |
169 | arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode, | |
170 | priv->bank); | |
171 | } | |
172 | ||
173 | static void arasan_sdhci_set_control_reg(struct sdhci_host *host) | |
174 | { | |
175 | struct mmc *mmc = (struct mmc *)host->mmc; | |
176 | u32 reg; | |
177 | ||
84333708 SDPP |
178 | if (!IS_SD(mmc)) |
179 | return; | |
180 | ||
d1f4e39d | 181 | if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { |
d1c0a220 FA |
182 | reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
183 | reg |= SDHCI_CTRL_VDD_180; | |
184 | sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); | |
d1f4e39d SDPP |
185 | } |
186 | ||
187 | if (mmc->selected_mode > SD_HS && | |
d1c0a220 FA |
188 | mmc->selected_mode <= UHS_DDR50) |
189 | sdhci_set_uhs_timing(host); | |
d1f4e39d SDPP |
190 | } |
191 | #endif | |
192 | ||
c95b19ac | 193 | #if defined(CONFIG_ARCH_ZYNQMP) |
d1f4e39d SDPP |
194 | const struct sdhci_ops arasan_ops = { |
195 | .platform_execute_tuning = &arasan_sdhci_execute_tuning, | |
196 | .set_delay = &arasan_sdhci_set_tapdelay, | |
197 | .set_control_reg = &arasan_sdhci_set_control_reg, | |
198 | }; | |
199 | #endif | |
200 | ||
d9ae52c8 | 201 | static int arasan_sdhci_probe(struct udevice *dev) |
293eb33f | 202 | { |
329a449f | 203 | struct arasan_sdhci_plat *plat = dev_get_platdata(dev); |
d9ae52c8 | 204 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
d1f4e39d SDPP |
205 | struct arasan_sdhci_priv *priv = dev_get_priv(dev); |
206 | struct sdhci_host *host; | |
e0f4de1a SH |
207 | struct clk clk; |
208 | unsigned long clock; | |
329a449f | 209 | int ret; |
293eb33f | 210 | |
d1f4e39d SDPP |
211 | host = priv->host; |
212 | ||
e0f4de1a SH |
213 | ret = clk_get_by_index(dev, 0, &clk); |
214 | if (ret < 0) { | |
215 | dev_err(dev, "failed to get clock\n"); | |
216 | return ret; | |
217 | } | |
218 | ||
219 | clock = clk_get_rate(&clk); | |
220 | if (IS_ERR_VALUE(clock)) { | |
221 | dev_err(dev, "failed to get rate\n"); | |
222 | return clock; | |
223 | } | |
d1f4e39d | 224 | |
e0f4de1a SH |
225 | debug("%s: CLK %ld\n", __func__, clock); |
226 | ||
227 | ret = clk_enable(&clk); | |
228 | if (ret && ret != -ENOSYS) { | |
229 | dev_err(dev, "failed to enable clock\n"); | |
230 | return ret; | |
231 | } | |
232 | ||
eddabd16 | 233 | host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | |
f9ec45d1 | 234 | SDHCI_QUIRK_BROKEN_R1B; |
b2156146 SDPP |
235 | |
236 | #ifdef CONFIG_ZYNQ_HISPD_BROKEN | |
47819216 | 237 | host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; |
b2156146 SDPP |
238 | #endif |
239 | ||
942b5fc0 BG |
240 | plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; |
241 | ||
242 | ret = mmc_of_parse(dev, &plat->cfg); | |
243 | if (ret) | |
244 | return ret; | |
d1f4e39d | 245 | |
e0f4de1a | 246 | host->max_clk = clock; |
6d0e34bf | 247 | |
3148a3c2 MK |
248 | host->mmc = &plat->mmc; |
249 | host->mmc->dev = dev; | |
250 | host->mmc->priv = host; | |
251 | ||
942b5fc0 | 252 | ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max, |
14bed52d | 253 | CONFIG_ZYNQ_SDHCI_MIN_FREQ); |
329a449f SG |
254 | if (ret) |
255 | return ret; | |
329a449f | 256 | upriv->mmc = host->mmc; |
d9ae52c8 | 257 | |
329a449f | 258 | return sdhci_probe(dev); |
293eb33f | 259 | } |
d9ae52c8 MS |
260 | |
261 | static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) | |
262 | { | |
d1f4e39d SDPP |
263 | struct arasan_sdhci_priv *priv = dev_get_priv(dev); |
264 | ||
265 | priv->host = calloc(1, sizeof(struct sdhci_host)); | |
266 | if (!priv->host) | |
267 | return -1; | |
d9ae52c8 | 268 | |
d1f4e39d | 269 | priv->host->name = dev->name; |
d1f4e39d | 270 | |
c95b19ac | 271 | #if defined(CONFIG_ARCH_ZYNQMP) |
d1f4e39d SDPP |
272 | priv->host->ops = &arasan_ops; |
273 | #endif | |
d9ae52c8 | 274 | |
458e8d80 MS |
275 | priv->host->ioaddr = (void *)dev_read_addr(dev); |
276 | if (IS_ERR(priv->host->ioaddr)) | |
277 | return PTR_ERR(priv->host->ioaddr); | |
61e745d1 | 278 | |
458e8d80 MS |
279 | priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); |
280 | priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1); | |
458e8d80 | 281 | |
d9ae52c8 MS |
282 | return 0; |
283 | } | |
284 | ||
329a449f SG |
285 | static int arasan_sdhci_bind(struct udevice *dev) |
286 | { | |
287 | struct arasan_sdhci_plat *plat = dev_get_platdata(dev); | |
329a449f | 288 | |
24f5aec3 | 289 | return sdhci_bind(dev, &plat->mmc, &plat->cfg); |
329a449f SG |
290 | } |
291 | ||
d9ae52c8 MS |
292 | static const struct udevice_id arasan_sdhci_ids[] = { |
293 | { .compatible = "arasan,sdhci-8.9a" }, | |
294 | { } | |
295 | }; | |
296 | ||
297 | U_BOOT_DRIVER(arasan_sdhci_drv) = { | |
298 | .name = "arasan_sdhci", | |
299 | .id = UCLASS_MMC, | |
300 | .of_match = arasan_sdhci_ids, | |
301 | .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, | |
329a449f SG |
302 | .ops = &sdhci_ops, |
303 | .bind = arasan_sdhci_bind, | |
d9ae52c8 | 304 | .probe = arasan_sdhci_probe, |
d1f4e39d | 305 | .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv), |
329a449f | 306 | .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat), |
d9ae52c8 | 307 | }; |