[u-boot.git] / drivers / misc / imx8 / scu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2018 NXP
 *
 * Peng Fan <[email protected]>
 */

#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
#include <asm/arch/sci/sci.h>
#include <linux/iopoll.h>
#include <misc.h>

DECLARE_GLOBAL_DATA_PTR;

struct mu_type {
	u32 tr[4];
	u32 rr[4];
	u32 sr;
	u32 cr;
};

struct imx8_scu {
	struct mu_type *base;
};

#define MU_CR_GIE_MASK		0xF0000000u
#define MU_CR_RIE_MASK		0xF000000u
#define MU_CR_GIR_MASK		0xF0000u
#define MU_CR_TIE_MASK		0xF00000u
#define MU_CR_F_MASK		0x7u
#define MU_SR_TE0_MASK		BIT(23)
#define MU_SR_RF0_MASK		BIT(27)
#define MU_TR_COUNT		4
#define MU_RR_COUNT		4

static inline void mu_hal_init(struct mu_type *base)
{
	/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
	clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
		     MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
}

static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
{
	u32 mask = MU_SR_TE0_MASK >> reg_index;
	u32 val;
	int ret;

	assert(reg_index < MU_TR_COUNT);

	/* Wait TX register to be empty. */
	ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
	if (ret < 0) {
		printf("%s timeout\n", __func__);
		return -ETIMEDOUT;
	}

	writel(msg, &base->tr[reg_index]);

	return 0;
}

static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
{
	u32 mask = MU_SR_RF0_MASK >> reg_index;
	u32 val;
	int ret;

	assert(reg_index < MU_TR_COUNT);

	/* Wait RX register to be full. */
	ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000);
	if (ret < 0) {
		printf("%s timeout\n", __func__);
		return -ETIMEDOUT;
	}

	*msg = readl(&base->rr[reg_index]);

	return 0;
}

static int sc_ipc_read(struct mu_type *base, void *data)
{
	struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
	int ret;
	u8 count = 0;

	if (!msg)
		return -EINVAL;

	/* Read first word */
	ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
	if (ret)
		return ret;
	count++;

	/* Check size */
	if (msg->size > SC_RPC_MAX_MSG) {
		*((u32 *)msg) = 0;
		return -EINVAL;
	}

	/* Read remaining words */
	while (count < msg->size) {
		ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
					&msg->DATA.u32[count - 1]);
		if (ret)
			return ret;
		count++;
	}

	return 0;
}

static int sc_ipc_write(struct mu_type *base, void *data)
{
	struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
	int ret;
	u8 count = 0;

	if (!msg)
		return -EINVAL;

	/* Check size */
	if (msg->size > SC_RPC_MAX_MSG)
		return -EINVAL;

	/* Write first word */
	ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
	if (ret)
		return ret;
	count++;

	/* Write remaining words */
	while (count < msg->size) {
		ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
				     msg->DATA.u32[count - 1]);
		if (ret)
			return ret;
		count++;
	}

	return 0;
}

/*
 * Note the function prototype use msgid as the 2nd parameter, here
 * we take it as no_resp.
 */
static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
			 int tx_size, void *rx_msg, int rx_size)
{
	struct imx8_scu *plat = dev_get_platdata(dev);
	sc_err_t result;
	int ret;

	/* Expect tx_msg, rx_msg are the same value */
	if (rx_msg && tx_msg != rx_msg)
		printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);

	ret = sc_ipc_write(plat->base, tx_msg);
	if (ret)
		return ret;
	if (!no_resp) {
		ret = sc_ipc_read(plat->base, rx_msg);
		if (ret)
			return ret;
	}

	result = RPC_R8((struct sc_rpc_msg_s *)tx_msg);

	return sc_err_to_linux(result);
}

static int imx8_scu_probe(struct udevice *dev)
{
	struct imx8_scu *plat = dev_get_platdata(dev);
	fdt_addr_t addr;

	debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

#ifdef CONFIG_SPL_BUILD
	plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
#else
	plat->base = (struct mu_type *)addr;
#endif

	/* U-Boot not enable interrupts, so need to enable RX interrupts */
	mu_hal_init(plat->base);

	gd->arch.scu_dev = dev;

	return 0;
}

static int imx8_scu_remove(struct udevice *dev)
{
	return 0;
}

static int imx8_scu_bind(struct udevice *dev)
{
	int ret;
	struct udevice *child;
	ofnode node;

	debug("%s(dev=%p)\n", __func__, dev);
	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
		ret = lists_bind_fdt(dev, node, &child, true);
		if (ret)
			return ret;
		debug("bind child dev %s\n", child->name);
	}

	return 0;
}

static struct misc_ops imx8_scu_ops = {
	.call = imx8_scu_call,
};

static const struct udevice_id imx8_scu_ids[] = {
	{ .compatible = "fsl,imx8qxp-mu" },
	{ .compatible = "fsl,imx8-mu" },
	{ }
};

U_BOOT_DRIVER(imx8_scu) = {
	.name		= "imx8_scu",
	.id		= UCLASS_MISC,
	.of_match	= imx8_scu_ids,
	.probe		= imx8_scu_probe,
	.bind		= imx8_scu_bind,
	.remove		= imx8_scu_remove,
	.ops		= &imx8_scu_ops,
	.platdata_auto_alloc_size = sizeof(struct imx8_scu),
	.flags		= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
ef64e782 PF	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright 2018 NXP
	4	*
	5	* Peng Fan <[email protected]>
	6	*/
	7
	8	#include <common.h>
f7ae49fc	9	#include <log.h>
ef64e782 PF	10	#include <asm/io.h>
	11	#include <dm.h>
	12	#include <dm/lists.h>
	13	#include <dm/root.h>
	14	#include <dm/device-internal.h>
	15	#include <asm/arch/sci/sci.h>
	16	#include <linux/iopoll.h>
	17	#include <misc.h>
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	struct mu_type {
	22	u32 tr[4];
	23	u32 rr[4];
	24	u32 sr;
	25	u32 cr;
	26	};
	27
	28	struct imx8_scu {
	29	struct mu_type *base;
ef64e782 PF	30	};
	31
	32	#define MU_CR_GIE_MASK 0xF0000000u
	33	#define MU_CR_RIE_MASK 0xF000000u
	34	#define MU_CR_GIR_MASK 0xF0000u
	35	#define MU_CR_TIE_MASK 0xF00000u
	36	#define MU_CR_F_MASK 0x7u
	37	#define MU_SR_TE0_MASK BIT(23)
	38	#define MU_SR_RF0_MASK BIT(27)
	39	#define MU_TR_COUNT 4
	40	#define MU_RR_COUNT 4
	41
	42	static inline void mu_hal_init(struct mu_type *base)
	43	{
	44	/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
	45	clrbits_le32(&base->cr, MU_CR_GIE_MASK \| MU_CR_RIE_MASK \|
	46	MU_CR_TIE_MASK \| MU_CR_GIR_MASK \| MU_CR_F_MASK);
	47	}
	48
	49	static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
	50	{
	51	u32 mask = MU_SR_TE0_MASK >> reg_index;
	52	u32 val;
	53	int ret;
	54
	55	assert(reg_index < MU_TR_COUNT);
	56
	57	/* Wait TX register to be empty. */
	58	ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
	59	if (ret < 0) {
	60	printf("%s timeout\n", __func__);
	61	return -ETIMEDOUT;
	62	}
	63
	64	writel(msg, &base->tr[reg_index]);
	65
	66	return 0;
	67	}
	68
	69	static int mu_hal_receivemsg(struct mu_type base, u32 reg_index, u32 msg)
	70	{
	71	u32 mask = MU_SR_RF0_MASK >> reg_index;
	72	u32 val;
	73	int ret;
	74
	75	assert(reg_index < MU_TR_COUNT);
	76
	77	/* Wait RX register to be full. */
77ed80c9	78	ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000);
ef64e782 PF	79	if (ret < 0) {
	80	printf("%s timeout\n", __func__);
	81	return -ETIMEDOUT;
	82	}
	83
	84	*msg = readl(&base->rr[reg_index]);
	85
	86	return 0;
	87	}
	88
	89	static int sc_ipc_read(struct mu_type base, void data)
	90	{
	91	struct sc_rpc_msg_s msg = (struct sc_rpc_msg_s )data;
	92	int ret;
	93	u8 count = 0;
	94
	95	if (!msg)
	96	return -EINVAL;
	97
	98	/* Read first word */
	99	ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
	100	if (ret)
	101	return ret;
	102	count++;
	103
	104	/* Check size */
	105	if (msg->size > SC_RPC_MAX_MSG) {
	106	((u32 )msg) = 0;
	107	return -EINVAL;
	108	}
	109
	110	/* Read remaining words */
	111	while (count < msg->size) {
	112	ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
	113	&msg->DATA.u32[count - 1]);
	114	if (ret)
	115	return ret;
	116	count++;
	117	}
	118
	119	return 0;
	120	}
	121
	122	static int sc_ipc_write(struct mu_type base, void data)
	123	{
	124	struct sc_rpc_msg_s msg = (struct sc_rpc_msg_s )data;
	125	int ret;
	126	u8 count = 0;
	127
	128	if (!msg)
	129	return -EINVAL;
	130
	131	/* Check size */
	132	if (msg->size > SC_RPC_MAX_MSG)
	133	return -EINVAL;
	134
	135	/* Write first word */
	136	ret = mu_hal_sendmsg(base, 0, ((u32 )msg));
	137	if (ret)
	138	return ret;
	139	count++;
	140
	141	/* Write remaining words */
	142	while (count < msg->size) {
143	ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
144	msg->DATA.u32[count - 1]);
145	if (ret)
146	return ret;
147	count++;
148	}
149
150	return 0;
151	}
152
153	/*
154	* Note the function prototype use msgid as the 2nd parameter, here
155	* we take it as no_resp.
156	*/
157	static int imx8_scu_call(struct udevice dev, int no_resp, void tx_msg,
158	int tx_size, void *rx_msg, int rx_size)
159	{
026381fc	160	struct imx8_scu *plat = dev_get_platdata(dev);
ef64e782 PF	161	sc_err_t result;
	162	int ret;
	163
	164	/* Expect tx_msg, rx_msg are the same value */
	165	if (rx_msg && tx_msg != rx_msg)
	166	printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
	167
026381fc	168	ret = sc_ipc_write(plat->base, tx_msg);
ef64e782 PF	169	if (ret)
	170	return ret;
	171	if (!no_resp) {
026381fc	172	ret = sc_ipc_read(plat->base, rx_msg);
ef64e782 PF	173	if (ret)
	174	return ret;
	175	}
	176
	177	result = RPC_R8((struct sc_rpc_msg_s *)tx_msg);
	178
	179	return sc_err_to_linux(result);
	180	}
	181
	182	static int imx8_scu_probe(struct udevice *dev)
	183	{
026381fc	184	struct imx8_scu *plat = dev_get_platdata(dev);
ef64e782 PF	185	fdt_addr_t addr;
ef64e782 PF	186
026381fc	187	debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
ef64e782 PF	188
	189	addr = devfdt_get_addr(dev);
	190	if (addr == FDT_ADDR_T_NONE)
	191	return -EINVAL;
	192
04b24965 PF	193	#ifdef CONFIG_SPL_BUILD
	194	plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
	195	#else
026381fc	196	plat->base = (struct mu_type *)addr;
04b24965	197	#endif
ef64e782 PF	198
ef64e782 PF	199	/* U-Boot not enable interrupts, so need to enable RX interrupts */
026381fc	200	mu_hal_init(plat->base);
ef64e782 PF	201
	202	gd->arch.scu_dev = dev;
	203
ef64e782 PF	204	return 0;
	205	}
	206
	207	static int imx8_scu_remove(struct udevice *dev)
	208	{
	209	return 0;
	210	}
	211
	212	static int imx8_scu_bind(struct udevice *dev)
	213	{
ef64e782 PF	214	int ret;
ef64e782 PF	215	struct udevice *child;
816d093c	216	ofnode node;
ef64e782 PF	217
ef64e782 PF	218	debug("%s(dev=%p)\n", __func__, dev);
816d093c PF	219	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
	220	ret = lists_bind_fdt(dev, node, &child, true);
	221	if (ret)
	222	return ret;
	223	debug("bind child dev %s\n", child->name);
	224	}
ef64e782 PF	225
	226	return 0;
	227	}
	228
	229	static struct misc_ops imx8_scu_ops = {
	230	.call = imx8_scu_call,
	231	};
	232
	233	static const struct udevice_id imx8_scu_ids[] = {
	234	{ .compatible = "fsl,imx8qxp-mu" },
	235	{ .compatible = "fsl,imx8-mu" },
	236	{ }
	237	};
	238
	239	U_BOOT_DRIVER(imx8_scu) = {
	240	.name = "imx8_scu",
	241	.id = UCLASS_MISC,
	242	.of_match = imx8_scu_ids,
	243	.probe = imx8_scu_probe,
	244	.bind = imx8_scu_bind,
	245	.remove = imx8_scu_remove,
	246	.ops = &imx8_scu_ops,
026381fc	247	.platdata_auto_alloc_size = sizeof(struct imx8_scu),
ef64e782 PF	248	.flags = DM_FLAG_PRE_RELOC,
ef64e782 PF	249	};