common: Drop log.h from common header
[u-boot.git] / arch / arm / mach-socfpga / spl_gen5.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
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2/*
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
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4 */
5
6#include <common.h>
db41d65a 7#include <hang.h>
691d719d 8#include <init.h>
f7ae49fc 9#include <log.h>
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10#include <asm/io.h>
11#include <asm/u-boot.h>
12#include <asm/utils.h>
77754408 13#include <image.h>
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14#include <asm/arch/reset_manager.h>
15#include <spl.h>
5d649d2b 16#include <asm/arch/system_manager.h>
4c544197 17#include <asm/arch/freeze_controller.h>
3ab019e1 18#include <asm/arch/clock_manager.h>
011fa5f3 19#include <asm/arch/misc.h>
3ab019e1 20#include <asm/arch/scan_manager.h>
37ef0c70 21#include <asm/arch/sdram.h>
8f4c80c4 22#include <asm/sections.h>
c0b4fc1a 23#include <debug_uart.h>
8f4c80c4
LFT
24#include <fdtdec.h>
25#include <watchdog.h>
29873c74 26#include <dm/uclass.h>
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27
28DECLARE_GLOBAL_DATA_PTR;
29
6473054a
MV
30u32 spl_boot_device(void)
31{
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32 const u32 bsel = readl(socfpga_get_sysmgr_addr() +
33 SYSMGR_GEN5_BOOTINFO);
066ad14a 34
8f4c80c4 35 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
066ad14a
MV
36 case 0x1: /* FPGA (HPS2FPGA Bridge) */
37 return BOOT_DEVICE_RAM;
38 case 0x2: /* NAND Flash (1.8V) */
39 case 0x3: /* NAND Flash (3.0V) */
40 return BOOT_DEVICE_NAND;
41 case 0x4: /* SD/MMC External Transceiver (1.8V) */
42 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
066ad14a
MV
43 return BOOT_DEVICE_MMC1;
44 case 0x6: /* QSPI Flash (1.8V) */
45 case 0x7: /* QSPI Flash (3.0V) */
066ad14a
MV
46 return BOOT_DEVICE_SPI;
47 default:
48 printf("Invalid boot device (bsel=%08x)!\n", bsel);
49 hang();
50 }
d3f34e75
MV
51}
52
c859f2a7 53#ifdef CONFIG_SPL_MMC_SUPPORT
e9759065 54u32 spl_mmc_boot_mode(const u32 boot_device)
c859f2a7 55{
f4b40924 56#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
c859f2a7
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57 return MMCSD_MODE_FS;
58#else
59 return MMCSD_MODE_RAW;
60#endif
61}
62#endif
63
0ef44d11
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64void board_init_f(ulong dummy)
65{
6473054a 66 const struct cm_config *cm_default_cfg = cm_get_default_config();
0ef44d11 67 unsigned long reg;
40c36f8d 68 int ret;
29873c74 69 struct udevice *dev;
6473054a 70
bb25aca1
LFT
71 ret = spl_early_init();
72 if (ret)
73 hang();
74
75 socfpga_get_managers_addr();
76
0ef44d11 77 /*
bb25aca1 78 * Clear fake OCRAM ECC first as SBE
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79 * and DBE might triggered during power on
80 */
db5741f7 81 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
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82 if (reg & SYSMGR_ECC_OCRAM_SERR)
83 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
db5741f7 84 socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
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85 if (reg & SYSMGR_ECC_OCRAM_DERR)
86 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
db5741f7 87 socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
0ef44d11 88
e4ff8420 89 socfpga_sdram_remap_zero();
4a9743f7 90 socfpga_pl310_clear();
0ef44d11 91
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CLS
92 debug("Freezing all I/O banks\n");
93 /* freeze all IO banks */
94 sys_mgr_frzctrl_freeze_req();
95
bd65fe35
MV
96 /* Put everything into reset but L4WD0. */
97 socfpga_per_reset_all();
30bade20
SG
98
99 if (!socfpga_is_booting_from_fpga()) {
100 /* Put FPGA bridges into reset too. */
101 socfpga_bridges_reset(1);
102 }
bd65fe35 103
a71df7aa 104 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
9fd565db
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105 timer_init();
106
ddfeb0aa
CLS
107 debug("Reconfigure Clock Manager\n");
108 /* reconfigure the PLLs */
de778115
LFT
109 if (cm_basic_init(cm_default_cfg))
110 hang();
ddfeb0aa 111
08e463ee 112 /* Enable bootrom to configure IOs. */
40687b4f 113 sysmgr_config_warmrstcfgio(1);
08e463ee 114
dc4d4aa1
CLS
115 /* configure the IOCSR / IO buffer settings */
116 if (scan_mgr_configure_iocsr())
117 hang();
118
4a0080d9
MV
119 sysmgr_config_warmrstcfgio(0);
120
5d649d2b 121 /* configure the pin muxing through system manager */
4a0080d9 122 sysmgr_config_warmrstcfgio(1);
5d649d2b 123 sysmgr_pinmux_init();
4a0080d9
MV
124 sysmgr_config_warmrstcfgio(0);
125
430b42f7 126 /* Set bridges handoff value */
c1d4b464 127 socfpga_bridges_set_handoff_regs(true, true, true);
77754408 128
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CLS
129 debug("Unfreezing/Thaw all I/O banks\n");
130 /* unfreeze / thaw all IO banks */
131 sys_mgr_frzctrl_thaw_req();
132
c0b4fc1a
SG
133#ifdef CONFIG_DEBUG_UART
134 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
135 debug_uart_init();
136#endif
137
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138 ret = uclass_get_device(UCLASS_RESET, 0, &dev);
139 if (ret)
140 debug("Reset init failed: %d\n", ret);
141
a1a9843a 142#ifdef CONFIG_SPL_NAND_DENALI
707c36e2 143 clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
a1a9843a
MV
144#endif
145
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146 /* enable console uart printing */
147 preloader_console_init();
37ef0c70 148
29873c74
SG
149 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
150 if (ret) {
151 debug("DRAM init failed: %d\n", ret);
9ad3a4ac
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152 hang();
153 }
77754408 154}
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