[u-boot.git] / arch / arm / mach-imx / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 */

#include <bootm.h>
#include <common.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <netdev.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/boot_mode.h>
#include <imx_thermal.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>

#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
#endif

static u32 reset_cause = -1;

u32 get_imx_reset_cause(void)
{
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;

	if (reset_cause == -1) {
		reset_cause = readl(&src_regs->srsr);
/* preserve the value for U-Boot proper */
#if !defined(CONFIG_SPL_BUILD)
		writel(reset_cause, &src_regs->srsr);
#endif
	}

	return reset_cause;
}

#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
static char *get_reset_cause(void)
{
	switch (get_imx_reset_cause()) {
	case 0x00001:
	case 0x00011:
		return "POR";
	case 0x00004:
		return "CSU";
	case 0x00008:
		return "IPP USER";
	case 0x00010:
#ifdef	CONFIG_MX7
		return "WDOG1";
#else
		return "WDOG";
#endif
	case 0x00020:
		return "JTAG HIGH-Z";
	case 0x00040:
		return "JTAG SW";
	case 0x00080:
		return "WDOG3";
#ifdef CONFIG_MX7
	case 0x00100:
		return "WDOG4";
	case 0x00200:
		return "TEMPSENSE";
#elif defined(CONFIG_IMX8M)
	case 0x00100:
		return "WDOG2";
	case 0x00200:
		return "TEMPSENSE";
#else
	case 0x00100:
		return "TEMPSENSE";
	case 0x10000:
		return "WARM BOOT";
#endif
	default:
		return "unknown reset";
	}
}
#endif

#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)

const char *get_imx_type(u32 imxtype)
{
	switch (imxtype) {
	case MXC_CPU_IMX8MP:
		return "8MP";	/* Quad-core version of the imx8mp */
	case MXC_CPU_IMX8MN:
		return "8MNano Quad"; /* Quad-core version */
	case MXC_CPU_IMX8MND:
		return "8MNano Dual"; /* Dual-core version */
	case MXC_CPU_IMX8MNS:
		return "8MNano Solo"; /* Single-core version */
	case MXC_CPU_IMX8MNL:
		return "8MNano QuadLite"; /* Quad-core Lite version */
	case MXC_CPU_IMX8MNDL:
		return "8MNano DualLite"; /* Dual-core Lite version */
	case MXC_CPU_IMX8MNSL:
		return "8MNano SoloLite"; /* Single-core Lite version */
	case MXC_CPU_IMX8MM:
		return "8MMQ";	/* Quad-core version of the imx8mm */
	case MXC_CPU_IMX8MML:
		return "8MMQL";	/* Quad-core Lite version of the imx8mm */
	case MXC_CPU_IMX8MMD:
		return "8MMD";	/* Dual-core version of the imx8mm */
	case MXC_CPU_IMX8MMDL:
		return "8MMDL";	/* Dual-core Lite version of the imx8mm */
	case MXC_CPU_IMX8MMS:
		return "8MMS";	/* Single-core version of the imx8mm */
	case MXC_CPU_IMX8MMSL:
		return "8MMSL";	/* Single-core Lite version of the imx8mm */
	case MXC_CPU_IMX8MQ:
		return "8MQ";	/* Quad-core version of the imx8mq */
	case MXC_CPU_IMX8MQL:
		return "8MQLite";	/* Quad-core Lite version of the imx8mq */
	case MXC_CPU_IMX8MD:
		return "8MD";	/* Dual-core version of the imx8mq */
	case MXC_CPU_MX7S:
		return "7S";	/* Single-core version of the mx7 */
	case MXC_CPU_MX7D:
		return "7D";	/* Dual-core version of the mx7 */
	case MXC_CPU_MX6QP:
		return "6QP";	/* Quad-Plus version of the mx6 */
	case MXC_CPU_MX6DP:
		return "6DP";	/* Dual-Plus version of the mx6 */
	case MXC_CPU_MX6Q:
		return "6Q";	/* Quad-core version of the mx6 */
	case MXC_CPU_MX6D:
		return "6D";	/* Dual-core version of the mx6 */
	case MXC_CPU_MX6DL:
		return "6DL";	/* Dual Lite version of the mx6 */
	case MXC_CPU_MX6SOLO:
		return "6SOLO";	/* Solo version of the mx6 */
	case MXC_CPU_MX6SL:
		return "6SL";	/* Solo-Lite version of the mx6 */
	case MXC_CPU_MX6SLL:
		return "6SLL";	/* SLL version of the mx6 */
	case MXC_CPU_MX6SX:
		return "6SX";   /* SoloX version of the mx6 */
	case MXC_CPU_MX6UL:
		return "6UL";   /* Ultra-Lite version of the mx6 */
	case MXC_CPU_MX6ULL:
		return "6ULL";	/* ULL version of the mx6 */
	case MXC_CPU_MX6ULZ:
		return "6ULZ";	/* ULZ version of the mx6 */
	case MXC_CPU_MX51:
		return "51";
	case MXC_CPU_MX53:
		return "53";
	default:
		return "??";
	}
}

int print_cpuinfo(void)
{
	u32 cpurev;
	__maybe_unused u32 max_freq;

	cpurev = get_cpu_rev();

#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
	struct udevice *thermal_dev;
	int cpu_tmp, minc, maxc, ret;

	printf("CPU:   Freescale i.MX%s rev%d.%d",
	       get_imx_type((cpurev & 0x1FF000) >> 12),
	       (cpurev & 0x000F0) >> 4,
	       (cpurev & 0x0000F) >> 0);
	max_freq = get_cpu_speed_grade_hz();
	if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
		printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	} else {
		printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
		       mxc_get_clock(MXC_ARM_CLK) / 1000000);
	}
#else
	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
		get_imx_type((cpurev & 0x1FF000) >> 12),
		(cpurev & 0x000F0) >> 4,
		(cpurev & 0x0000F) >> 0,
		mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif

#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
	puts("CPU:   ");
	switch (get_cpu_temp_grade(&minc, &maxc)) {
	case TEMP_AUTOMOTIVE:
		puts("Automotive temperature grade ");
		break;
	case TEMP_INDUSTRIAL:
		puts("Industrial temperature grade ");
		break;
	case TEMP_EXTCOMMERCIAL:
		puts("Extended Commercial temperature grade ");
		break;
	default:
		puts("Commercial temperature grade ");
		break;
	}
	printf("(%dC to %dC)", minc, maxc);
	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	if (!ret) {
		ret = thermal_get_temp(thermal_dev, &cpu_tmp);

		if (!ret)
			printf(" at %dC\n", cpu_tmp);
		else
			debug(" - invalid sensor data\n");
	} else {
		debug(" - invalid sensor device\n");
	}
#endif

	printf("Reset cause: %s\n", get_reset_cause());
	return 0;
}
#endif

int cpu_eth_init(bd_t *bis)
{
	int rc = -ENODEV;

#if defined(CONFIG_FEC_MXC)
	rc = fecmxc_initialize(bis);
#endif

	return rc;
}

#ifdef CONFIG_FSL_ESDHC_IMX
/*
 * Initializes on-chip MMC controllers.
 * to override, implement board_mmc_init()
 */
int cpu_mmc_init(bd_t *bis)
{
	return fsl_esdhc_mmc_init(bis);
}
#endif

#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
u32 get_ahb_clk(void)
{
	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, ahb_podf;

	reg = __raw_readl(&imx_ccm->cbcdr);
	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;

	return get_periph_clk() / (ahb_podf + 1);
}
#endif

void arch_preboot_os(void)
{
#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
	imx_pcie_remove();
#endif
#if defined(CONFIG_SATA)
	if (!is_mx6sdl()) {
		sata_remove(0);
#if defined(CONFIG_MX6)
		disable_sata_clock();
#endif
	}
#endif
#if defined(CONFIG_VIDEO_IPUV3)
	/* disable video before launching O/S */
	ipuv3_fb_shutdown();
#endif
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
	lcdif_power_down();
#endif
}

#ifndef CONFIG_IMX8M
void set_chipselect_size(int const cs_size)
{
	unsigned int reg;
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	reg = readl(&iomuxc_regs->gpr[1]);

	switch (cs_size) {
	case CS0_128:
		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
		reg |= 0x5;
		break;
	case CS0_64M_CS1_64M:
		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
		reg |= 0x1B;
		break;
	case CS0_64M_CS1_32M_CS2_32M:
		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
		reg |= 0x4B;
		break;
	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
		reg |= 0x249;
		break;
	default:
		printf("Unknown chip select size: %d\n", cs_size);
		break;
	}

	writel(reg, &iomuxc_regs->gpr[1]);
}
#endif

#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
/*
 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_TESTER3_SPEED_SHIFT	8
enum cpu_speed {
	OCOTP_TESTER3_SPEED_GRADE0,
	OCOTP_TESTER3_SPEED_GRADE1,
	OCOTP_TESTER3_SPEED_GRADE2,
	OCOTP_TESTER3_SPEED_GRADE3,
	OCOTP_TESTER3_SPEED_GRADE4,
};

u32 get_cpu_speed_grade_hz(void)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->tester3);
	val >>= OCOTP_TESTER3_SPEED_SHIFT;

	if (is_imx8mn() || is_imx8mp()) {
		val &= 0xf;
		return 2300000000 - val * 100000000;
	}

	if (is_imx8mm())
		val &= 0x7;
	else
		val &= 0x3;

	switch(val) {
	case OCOTP_TESTER3_SPEED_GRADE0:
		return 800000000;
	case OCOTP_TESTER3_SPEED_GRADE1:
		return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
	case OCOTP_TESTER3_SPEED_GRADE2:
		return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
	case OCOTP_TESTER3_SPEED_GRADE3:
		return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
	case OCOTP_TESTER3_SPEED_GRADE4:
		return 2000000000;
	}

	return 0;
}

/*
 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_TESTER3_TEMP_SHIFT	6

u32 get_cpu_temp_grade(int *minc, int *maxc)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->tester3);
	val >>= OCOTP_TESTER3_TEMP_SHIFT;
	val &= 0x3;

	if (minc && maxc) {
		if (val == TEMP_AUTOMOTIVE) {
			*minc = -40;
			*maxc = 125;
		} else if (val == TEMP_INDUSTRIAL) {
			*minc = -40;
			*maxc = 105;
		} else if (val == TEMP_EXTCOMMERCIAL) {
			*minc = -20;
			*maxc = 105;
		} else {
			*minc = 0;
			*maxc = 95;
		}
	}
	return val;
}
#endif

#if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
enum boot_device get_boot_device(void)
{
	struct bootrom_sw_info **p =
		(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;

	enum boot_device boot_dev = SD1_BOOT;
	u8 boot_type = (*p)->boot_dev_type;
	u8 boot_instance = (*p)->boot_dev_instance;

	switch (boot_type) {
	case BOOT_TYPE_SD:
		boot_dev = boot_instance + SD1_BOOT;
		break;
	case BOOT_TYPE_MMC:
		boot_dev = boot_instance + MMC1_BOOT;
		break;
	case BOOT_TYPE_NAND:
		boot_dev = NAND_BOOT;
		break;
	case BOOT_TYPE_QSPI:
		boot_dev = QSPI_BOOT;
		break;
	case BOOT_TYPE_WEIM:
		boot_dev = WEIM_NOR_BOOT;
		break;
	case BOOT_TYPE_SPINOR:
		boot_dev = SPI_NOR_BOOT;
		break;
#ifdef CONFIG_IMX8M
	case BOOT_TYPE_USB:
		boot_dev = USB_BOOT;
		break;
#endif
	default:
		break;
	}

	return boot_dev;
}
#endif

#ifdef CONFIG_NXP_BOARD_REVISION
int nxp_board_rev(void)
{
	/*
	 * Get Board ID information from OCOTP_GP1[15:8]
	 * RevA: 0x1
	 * RevB: 0x2
	 * RevC: 0x3
	 */
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	return (readl(&fuse->gp1) >> 8 & 0x0F);
}

char nxp_board_rev_string(void)
{
	const char *rev = "A";

	return (*rev + nxp_board_rev() - 1);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
18936ee2 JL	2	/*
	3	* (C) Copyright 2007
	4	* Sascha Hauer, Pengutronix
	5	*
	6	* (C) Copyright 2009 Freescale Semiconductor, Inc.
18936ee2 JL	7	*/
18936ee2 JL	8
5624c6bd	9	#include <bootm.h>
18936ee2	10	#include <common.h>
691d719d	11	#include <init.h>
f7ae49fc	12	#include <log.h>
90526e9f	13	#include <net.h>
5624c6bd	14	#include <netdev.h>
1221ce45	15	#include <linux/errno.h>
18936ee2 JL	16	#include <asm/io.h>
	17	#include <asm/arch/imx-regs.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/sys_proto.h>
6a376046	20	#include <asm/arch/crm_regs.h>
770611f2	21	#include <asm/mach-imx/boot_mode.h>
70caa8e2	22	#include <imx_thermal.h>
e1eb75b5	23	#include <ipu_pixfmt.h>
7a264168	24	#include <thermal.h>
44b9841d	25	#include <sata.h>
18936ee2	26
e37ac717 YL	27	#ifdef CONFIG_FSL_ESDHC_IMX
e37ac717 YL	28	#include <fsl_esdhc_imx.h>
18936ee2 JL	29	#endif
18936ee2 JL	30
11c2e505 EN	31	static u32 reset_cause = -1;
11c2e505 EN	32
6ed4d26c	33	u32 get_imx_reset_cause(void)
18936ee2	34	{
18936ee2 JL	35	struct src src_regs = (struct src )SRC_BASE_ADDR;
18936ee2 JL	36
6ed4d26c MK	37	if (reset_cause == -1) {
	38	reset_cause = readl(&src_regs->srsr);
	39	/* preserve the value for U-Boot proper */
	40	#if !defined(CONFIG_SPL_BUILD)
	41	writel(reset_cause, &src_regs->srsr);
	42	#endif
	43	}
	44
	45	return reset_cause;
	46	}
18936ee2	47
6ed4d26c MK	48	#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
	49	static char *get_reset_cause(void)
	50	{
	51	switch (get_imx_reset_cause()) {
18936ee2	52	case 0x00001:
cece2622	53	case 0x00011:
18936ee2 JL	54	return "POR";
	55	case 0x00004:
	56	return "CSU";
	57	case 0x00008:
	58	return "IPP USER";
	59	case 0x00010:
cd562c8d AA	60	#ifdef CONFIG_MX7
	61	return "WDOG1";
	62	#else
18936ee2	63	return "WDOG";
cd562c8d	64	#endif
18936ee2 JL	65	case 0x00020:
	66	return "JTAG HIGH-Z";
	67	case 0x00040:
	68	return "JTAG SW";
cd562c8d AA	69	case 0x00080:
	70	return "WDOG3";
	71	#ifdef CONFIG_MX7
	72	case 0x00100:
	73	return "WDOG4";
	74	case 0x00200:
	75	return "TEMPSENSE";
cd357ad1	76	#elif defined(CONFIG_IMX8M)
7537e932 PF	77	case 0x00100:
	78	return "WDOG2";
	79	case 0x00200:
	80	return "TEMPSENSE";
cd562c8d AA	81	#else
	82	case 0x00100:
	83	return "TEMPSENSE";
18936ee2 JL	84	case 0x10000:
18936ee2 JL	85	return "WARM BOOT";
cd562c8d	86	#endif
18936ee2 JL	87	default:
	88	return "unknown reset";
	89	}
	90	}
28420e78	91	#endif
11c2e505	92
38df3701	93	#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
a7683867	94
20332a06	95	const char *get_imx_type(u32 imxtype)
a7683867 FE	96	{
a7683867 FE	97	switch (imxtype) {
625b03d8 PF	98	case MXC_CPU_IMX8MP:
625b03d8 PF	99	return "8MP"; /* Quad-core version of the imx8mp */
2434131a	100	case MXC_CPU_IMX8MN:
c9154032 PF	101	return "8MNano Quad"; /* Quad-core version */
	102	case MXC_CPU_IMX8MND:
	103	return "8MNano Dual"; /* Dual-core version */
	104	case MXC_CPU_IMX8MNS:
	105	return "8MNano Solo"; /* Single-core version */
	106	case MXC_CPU_IMX8MNL:
	107	return "8MNano QuadLite"; /* Quad-core Lite version */
	108	case MXC_CPU_IMX8MNDL:
	109	return "8MNano DualLite"; /* Dual-core Lite version */
	110	case MXC_CPU_IMX8MNSL:
	111	return "8MNano SoloLite"; /* Single-core Lite version */
65a6c500 PF	112	case MXC_CPU_IMX8MM:
	113	return "8MMQ"; /* Quad-core version of the imx8mm */
	114	case MXC_CPU_IMX8MML:
	115	return "8MMQL"; /* Quad-core Lite version of the imx8mm */
	116	case MXC_CPU_IMX8MMD:
	117	return "8MMD"; /* Dual-core version of the imx8mm */
	118	case MXC_CPU_IMX8MMDL:
	119	return "8MMDL"; /* Dual-core Lite version of the imx8mm */
	120	case MXC_CPU_IMX8MMS:
	121	return "8MMS"; /* Single-core version of the imx8mm */
	122	case MXC_CPU_IMX8MMSL:
	123	return "8MMSL"; /* Single-core Lite version of the imx8mm */
cd357ad1	124	case MXC_CPU_IMX8MQ:
cb1a1de6 PF	125	return "8MQ"; /* Quad-core version of the imx8mq */
	126	case MXC_CPU_IMX8MQL:
	127	return "8MQLite"; /* Quad-core Lite version of the imx8mq */
	128	case MXC_CPU_IMX8MD:
	129	return "8MD"; /* Dual-core version of the imx8mq */
e25a0656	130	case MXC_CPU_MX7S:
249092fa	131	return "7S"; /* Single-core version of the mx7 */
cd562c8d AA	132	case MXC_CPU_MX7D:
cd562c8d AA	133	return "7D"; /* Dual-core version of the mx7 */
d0acd993 PF	134	case MXC_CPU_MX6QP:
	135	return "6QP"; /* Quad-Plus version of the mx6 */
	136	case MXC_CPU_MX6DP:
	137	return "6DP"; /* Dual-Plus version of the mx6 */
20332a06	138	case MXC_CPU_MX6Q:
a7683867	139	return "6Q"; /* Quad-core version of the mx6 */
94db6655 FE	140	case MXC_CPU_MX6D:
94db6655 FE	141	return "6D"; /* Dual-core version of the mx6 */
20332a06 TK	142	case MXC_CPU_MX6DL:
	143	return "6DL"; /* Dual Lite version of the mx6 */
	144	case MXC_CPU_MX6SOLO:
	145	return "6SOLO"; /* Solo version of the mx6 */
	146	case MXC_CPU_MX6SL:
a7683867	147	return "6SL"; /* Solo-Lite version of the mx6 */
7ce6d3c8 PF	148	case MXC_CPU_MX6SLL:
7ce6d3c8 PF	149	return "6SLL"; /* SLL version of the mx6 */
05d54b82 FE	150	case MXC_CPU_MX6SX:
05d54b82 FE	151	return "6SX"; /* SoloX version of the mx6 */
8631c06e PF	152	case MXC_CPU_MX6UL:
8631c06e PF	153	return "6UL"; /* Ultra-Lite version of the mx6 */
65ce54be PF	154	case MXC_CPU_MX6ULL:
65ce54be PF	155	return "6ULL"; /* ULL version of the mx6 */
81ae46c2 PF	156	case MXC_CPU_MX6ULZ:
81ae46c2 PF	157	return "6ULZ"; /* ULZ version of the mx6 */
20332a06	158	case MXC_CPU_MX51:
a7683867	159	return "51";
20332a06	160	case MXC_CPU_MX53:
a7683867 FE	161	return "53";
a7683867 FE	162	default:
e972d72b	163	return "??";
a7683867 FE	164	}
	165	}
	166
18936ee2 JL	167	int print_cpuinfo(void)
18936ee2 JL	168	{
943a3f2c SB	169	u32 cpurev;
943a3f2c SB	170	__maybe_unused u32 max_freq;
18936ee2	171
1368f993 AA	172	cpurev = get_cpu_rev();
1368f993 AA	173
dc597d1d	174	#if defined(CONFIG_IMX_THERMAL) \|\| defined(CONFIG_IMX_TMU)
7a264168	175	struct udevice *thermal_dev;
70caa8e2	176	int cpu_tmp, minc, maxc, ret;
a7683867	177
b83ddac8	178	printf("CPU: Freescale i.MX%s rev%d.%d",
13868eaf	179	get_imx_type((cpurev & 0x1FF000) >> 12),
b83ddac8 TH	180	(cpurev & 0x000F0) >> 4,
	181	(cpurev & 0x0000F) >> 0);
	182	max_freq = get_cpu_speed_grade_hz();
	183	if (!max_freq \|\| max_freq == mxc_get_clock(MXC_ARM_CLK)) {
	184	printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
	185	} else {
	186	printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
	187	mxc_get_clock(MXC_ARM_CLK) / 1000000);
	188	}
	189	#else
a7683867	190	printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
13868eaf	191	get_imx_type((cpurev & 0x1FF000) >> 12),
18936ee2 JL	192	(cpurev & 0x000F0) >> 4,
	193	(cpurev & 0x0000F) >> 0,
	194	mxc_get_clock(MXC_ARM_CLK) / 1000000);
b83ddac8	195	#endif
7a264168	196
dc597d1d	197	#if defined(CONFIG_IMX_THERMAL) \|\| defined(CONFIG_IMX_TMU)
70caa8e2 TH	198	puts("CPU: ");
	199	switch (get_cpu_temp_grade(&minc, &maxc)) {
	200	case TEMP_AUTOMOTIVE:
	201	puts("Automotive temperature grade ");
	202	break;
	203	case TEMP_INDUSTRIAL:
	204	puts("Industrial temperature grade ");
	205	break;
	206	case TEMP_EXTCOMMERCIAL:
	207	puts("Extended Commercial temperature grade ");
	208	break;
	209	default:
	210	puts("Commercial temperature grade ");
	211	break;
	212	}
	213	printf("(%dC to %dC)", minc, maxc);
7a264168 YL	214	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
	215	if (!ret) {
	216	ret = thermal_get_temp(thermal_dev, &cpu_tmp);
	217
	218	if (!ret)
70caa8e2	219	printf(" at %dC\n", cpu_tmp);
7a264168	220	else
3a384b49	221	debug(" - invalid sensor data\n");
7a264168	222	} else {
3a384b49	223	debug(" - invalid sensor device\n");
7a264168 YL	224	}
	225	#endif
	226
18936ee2 JL	227	printf("Reset cause: %s\n", get_reset_cause());
	228	return 0;
	229	}
	230	#endif
	231
	232	int cpu_eth_init(bd_t *bis)
	233	{
	234	int rc = -ENODEV;
	235
	236	#if defined(CONFIG_FEC_MXC)
	237	rc = fecmxc_initialize(bis);
	238	#endif
	239
	240	return rc;
	241	}
	242
e37ac717	243	#ifdef CONFIG_FSL_ESDHC_IMX
18936ee2 JL	244	/*
	245	* Initializes on-chip MMC controllers.
	246	* to override, implement board_mmc_init()
	247	*/
	248	int cpu_mmc_init(bd_t *bis)
	249	{
18936ee2	250	return fsl_esdhc_mmc_init(bis);
18936ee2	251	}
ecb0f317	252	#endif
18936ee2	253
cd357ad1	254	#if !(defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8M))
6a376046 FE	255	u32 get_ahb_clk(void)
	256	{
	257	struct mxc_ccm_reg imx_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	258	u32 reg, ahb_podf;
	259
	260	reg = __raw_readl(&imx_ccm->cbcdr);
	261	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
	262	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
	263
	264	return get_periph_clk() / (ahb_podf + 1);
	265	}
cd562c8d	266	#endif
e1eb75b5	267
e1eb75b5 EN	268	void arch_preboot_os(void)
e1eb75b5 EN	269	{
42dc1230	270	#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
6ecbe137 TH	271	imx_pcie_remove();
6ecbe137 TH	272	#endif
10e40d54	273	#if defined(CONFIG_SATA)
86e59530 LZ	274	if (!is_mx6sdl()) {
86e59530 LZ	275	sata_remove(0);
dd1c8f1b	276	#if defined(CONFIG_MX6)
86e59530	277	disable_sata_clock();
dd1c8f1b	278	#endif
86e59530	279	}
44b9841d NK	280	#endif
44b9841d NK	281	#if defined(CONFIG_VIDEO_IPUV3)
e1eb75b5 EN	282	/* disable video before launching O/S */
e1eb75b5 EN	283	ipuv3_fb_shutdown();
e1eb75b5	284	#endif
8c1df09f	285	#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
623787fd PF	286	lcdif_power_down();
623787fd PF	287	#endif
44b9841d	288	}
32c81ea6	289
cd357ad1	290	#ifndef CONFIG_IMX8M
32c81ea6 FE	291	void set_chipselect_size(int const cs_size)
	292	{
	293	unsigned int reg;
	294	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	295	reg = readl(&iomuxc_regs->gpr[1]);
	296
	297	switch (cs_size) {
	298	case CS0_128:
	299	reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
	300	reg \|= 0x5;
	301	break;
	302	case CS0_64M_CS1_64M:
	303	reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
	304	reg \|= 0x1B;
	305	break;
	306	case CS0_64M_CS1_32M_CS2_32M:
	307	reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
	308	reg \|= 0x4B;
	309	break;
	310	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
	311	reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
	312	reg \|= 0x249;
	313	break;
	314	default:
	315	printf("Unknown chip select size: %d\n", cs_size);
	316	break;
	317	}
	318
	319	writel(reg, &iomuxc_regs->gpr[1]);
	320	}
7537e932	321	#endif
4555c261	322
cd357ad1	323	#if defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8M)
423e84bc PF	324	/*
	325	* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
	326	* defines a 2-bit SPEED_GRADING
	327	*/
	328	#define OCOTP_TESTER3_SPEED_SHIFT 8
e56d9d79 PF	329	enum cpu_speed {
	330	OCOTP_TESTER3_SPEED_GRADE0,
	331	OCOTP_TESTER3_SPEED_GRADE1,
	332	OCOTP_TESTER3_SPEED_GRADE2,
	333	OCOTP_TESTER3_SPEED_GRADE3,
47586a4a	334	OCOTP_TESTER3_SPEED_GRADE4,
e56d9d79	335	};
423e84bc PF	336
	337	u32 get_cpu_speed_grade_hz(void)
	338	{
	339	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	340	struct fuse_bank *bank = &ocotp->bank[1];
	341	struct fuse_bank1_regs *fuse =
	342	(struct fuse_bank1_regs *)bank->fuse_regs;
	343	uint32_t val;
	344
	345	val = readl(&fuse->tester3);
	346	val >>= OCOTP_TESTER3_SPEED_SHIFT;
47586a4a	347
354dcce6	348	if (is_imx8mn() \|\| is_imx8mp()) {
47586a4a PF	349	val &= 0xf;
	350	return 2300000000 - val * 100000000;
	351	}
	352
	353	if (is_imx8mm())
	354	val &= 0x7;
	355	else
	356	val &= 0x3;
423e84bc PF	357
423e84bc PF	358	switch(val) {
e56d9d79	359	case OCOTP_TESTER3_SPEED_GRADE0:
423e84bc	360	return 800000000;
e56d9d79	361	case OCOTP_TESTER3_SPEED_GRADE1:
c9a1a24b	362	return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
e56d9d79	363	case OCOTP_TESTER3_SPEED_GRADE2:
c9a1a24b	364	return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
e56d9d79	365	case OCOTP_TESTER3_SPEED_GRADE3:
c9a1a24b	366	return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
47586a4a PF	367	case OCOTP_TESTER3_SPEED_GRADE4:
47586a4a PF	368	return 2000000000;
423e84bc	369	}
e56d9d79	370
423e84bc PF	371	return 0;
	372	}
	373
	374	/*
	375	* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
	376	* defines a 2-bit SPEED_GRADING
	377	*/
	378	#define OCOTP_TESTER3_TEMP_SHIFT 6
	379
	380	u32 get_cpu_temp_grade(int minc, int maxc)
	381	{
	382	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	383	struct fuse_bank *bank = &ocotp->bank[1];
	384	struct fuse_bank1_regs *fuse =
	385	(struct fuse_bank1_regs *)bank->fuse_regs;
	386	uint32_t val;
	387
	388	val = readl(&fuse->tester3);
	389	val >>= OCOTP_TESTER3_TEMP_SHIFT;
	390	val &= 0x3;
	391
	392	if (minc && maxc) {
	393	if (val == TEMP_AUTOMOTIVE) {
	394	*minc = -40;
	395	*maxc = 125;
	396	} else if (val == TEMP_INDUSTRIAL) {
	397	*minc = -40;
	398	*maxc = 105;
	399	} else if (val == TEMP_EXTCOMMERCIAL) {
	400	*minc = -20;
	401	*maxc = 105;
	402	} else {
	403	*minc = 0;
	404	*maxc = 95;
	405	}
	406	}
	407	return val;
	408	}
	409	#endif
	410
b890c4ae	411	#if defined(CONFIG_MX7) \|\| defined(CONFIG_IMX8MQ) \|\| defined(CONFIG_IMX8MM)
770611f2 PF	412	enum boot_device get_boot_device(void)
	413	{
	414	struct bootrom_sw_info **p =
	415	(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
	416
	417	enum boot_device boot_dev = SD1_BOOT;
	418	u8 boot_type = (*p)->boot_dev_type;
	419	u8 boot_instance = (*p)->boot_dev_instance;
	420
	421	switch (boot_type) {
	422	case BOOT_TYPE_SD:
	423	boot_dev = boot_instance + SD1_BOOT;
	424	break;
	425	case BOOT_TYPE_MMC:
	426	boot_dev = boot_instance + MMC1_BOOT;
	427	break;
	428	case BOOT_TYPE_NAND:
	429	boot_dev = NAND_BOOT;
	430	break;
	431	case BOOT_TYPE_QSPI:
	432	boot_dev = QSPI_BOOT;
	433	break;
	434	case BOOT_TYPE_WEIM:
	435	boot_dev = WEIM_NOR_BOOT;
	436	break;
	437	case BOOT_TYPE_SPINOR:
	438	boot_dev = SPI_NOR_BOOT;
	439	break;
cd357ad1	440	#ifdef CONFIG_IMX8M
80ebf86d PF	441	case BOOT_TYPE_USB:
	442	boot_dev = USB_BOOT;
	443	break;
	444	#endif
770611f2 PF	445	default:
	446	break;
	447	}
	448
	449	return boot_dev;
	450	}
	451	#endif
	452
4555c261 FE	453	#ifdef CONFIG_NXP_BOARD_REVISION
	454	int nxp_board_rev(void)
	455	{
	456	/*
	457	* Get Board ID information from OCOTP_GP1[15:8]
	458	* RevA: 0x1
	459	* RevB: 0x2
	460	* RevC: 0x3
	461	*/
	462	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	463	struct fuse_bank *bank = &ocotp->bank[4];
	464	struct fuse_bank4_regs *fuse =
	465	(struct fuse_bank4_regs *)bank->fuse_regs;
	466
	467	return (readl(&fuse->gp1) >> 8 & 0x0F);
	468	}
	469
	470	char nxp_board_rev_string(void)
	471	{
	472	const char *rev = "A";
	473
	474	return (*rev + nxp_board_rev() - 1);
	475	}
	476	#endif