[u-boot.git] / drivers / spi / ich.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (c) 2011 The Chromium OS Authors.
 *
 * This file is derived from the flashrom project.
 */

#ifndef _ICH_H_
#define _ICH_H_

#include <linux/bitops.h>
struct ich7_spi_regs {
	uint16_t spis;
	uint16_t spic;
	uint32_t spia;
	uint64_t spid[8];
	uint64_t _pad;
	uint32_t bbar;
	uint16_t preop;
	uint16_t optype;
	uint8_t opmenu[8];
} __packed;

struct ich9_spi_regs {
	uint32_t bfpr;		/* 0x00 */
	uint16_t hsfs;
	uint16_t hsfc;
	uint32_t faddr;
	uint32_t _reserved0;
	uint32_t fdata[16];	/* 0x10 */
	uint32_t frap;		/* 0x50 */
	uint32_t freg[5];
	uint32_t _reserved1[3];
	uint32_t pr[5];		/* 0x74 */
	uint32_t _reserved2[2];
	uint8_t ssfs;		/* 0x90 */
	uint8_t ssfc[3];
	uint16_t preop;		/* 0x94 */
	uint16_t optype;
	uint8_t opmenu[8];	/* 0x98 */
	uint32_t bbar;
	uint8_t _reserved3[12];
	uint32_t fdoc;		/* 0xb0 */
	uint32_t fdod;
	uint8_t _reserved4[8];
	uint32_t afc;		/* 0xc0 */
	uint32_t lvscc;
	uint32_t uvscc;
	uint8_t _reserved5[4];
	uint32_t fpb;		/* 0xd0 */
	uint8_t _reserved6[28];
	uint32_t srdl;		/* 0xf0 */
	uint32_t srdc;
	uint32_t scs;
	uint32_t bcr;
} __packed;

enum {
	SPIS_SCIP =		0x0001,
	SPIS_GRANT =		0x0002,
	SPIS_CDS =		0x0004,
	SPIS_FCERR =		0x0008,
	SSFS_AEL =		0x0010,
	SPIS_LOCK =		0x8000,
	SPIS_RESERVED_MASK =	0x7ff0,
	SSFS_RESERVED_MASK =	0x7fe2
};

enum {
	SPIC_SCGO =		0x000002,
	SPIC_ACS =		0x000004,
	SPIC_SPOP =		0x000008,
	SPIC_DBC =		0x003f00,
	SPIC_DS =		0x004000,
	SPIC_SME =		0x008000,
	SSFC_SCF_MASK =		0x070000,
	SSFC_RESERVED =		0xf80000,

	/* Mask for speed byte, biuts 23:16 of SSFC */
	SSFC_SCF_33MHZ	=	0x01,
};

enum {
	HSFS_FDONE =		0x0001,
	HSFS_FCERR =		0x0002,
	HSFS_AEL =		0x0004,
	HSFS_BERASE_MASK =	0x0018,
	HSFS_BERASE_SHIFT =	3,
	HSFS_SCIP =		0x0020,
	HSFS_FDOPSS =		0x2000,
	HSFS_FDV =		0x4000,
	HSFS_FLOCKDN =		0x8000
};

enum {
	HSFC_FGO =		0x0001,
	HSFC_FCYCLE_MASK =	0x0006,
	HSFC_FCYCLE_SHIFT =	1,
	HSFC_FDBC_MASK =	0x3f00,
	HSFC_FDBC_SHIFT =	8,
	HSFC_FSMIE =		0x8000
};

struct spi_trans {
	uint8_t cmd;
	const uint8_t *out;
	uint32_t bytesout;
	uint8_t *in;
	uint32_t bytesin;
	uint8_t type;
	uint8_t opcode;
	uint32_t offset;
};

#define SPI_OPCODE_WRSR		0x01
#define SPI_OPCODE_PAGE_PROGRAM	0x02
#define SPI_OPCODE_READ		0x03
#define SPI_OPCODE_WRDIS	0x04
#define SPI_OPCODE_RDSR		0x05
#define SPI_OPCODE_WREN		0x06
#define SPI_OPCODE_FAST_READ	0x0b
#define SPI_OPCODE_ERASE_SECT	0x20
#define SPI_OPCODE_READ_ID	0x9f
#define SPI_OPCODE_ERASE_BLOCK	0xd8

#define SPI_OPCODE_TYPE_READ_NO_ADDRESS		0
#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS	1
#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS	2
#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS	3

#define SPI_OPMENU_0	SPI_OPCODE_WRSR
#define SPI_OPTYPE_0	SPI_OPCODE_TYPE_WRITE_NO_ADDRESS

#define SPI_OPMENU_1	SPI_OPCODE_PAGE_PROGRAM
#define SPI_OPTYPE_1	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS

#define SPI_OPMENU_2	SPI_OPCODE_READ
#define SPI_OPTYPE_2	SPI_OPCODE_TYPE_READ_WITH_ADDRESS

#define SPI_OPMENU_3	SPI_OPCODE_RDSR
#define SPI_OPTYPE_3	SPI_OPCODE_TYPE_READ_NO_ADDRESS

#define SPI_OPMENU_4	SPI_OPCODE_ERASE_SECT
#define SPI_OPTYPE_4	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS

#define SPI_OPMENU_5	SPI_OPCODE_READ_ID
#define SPI_OPTYPE_5	SPI_OPCODE_TYPE_READ_NO_ADDRESS

#define SPI_OPMENU_6	SPI_OPCODE_ERASE_BLOCK
#define SPI_OPTYPE_6	SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS

#define SPI_OPMENU_7	SPI_OPCODE_FAST_READ
#define SPI_OPTYPE_7	SPI_OPCODE_TYPE_READ_WITH_ADDRESS

#define SPI_OPPREFIX	((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
#define SPI_OPTYPE	((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
			 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
			 (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
			 (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))

#define ICH_BOUNDARY	0x1000

#define HSFSTS_FDBC_SHIFT	24
#define HSFSTS_FDBC_MASK	(0x3f << HSFSTS_FDBC_SHIFT)
#define HSFSTS_WET		BIT(21)
#define HSFSTS_FCYCLE_SHIFT	17
#define HSFSTS_FCYCLE_MASK	(0xf << HSFSTS_FCYCLE_SHIFT)

/* Supported flash cycle types */
enum hsfsts_cycle_t {
	HSFSTS_CYCLE_READ	= 0,
	HSFSTS_CYCLE_WRITE	= 2,
	HSFSTS_CYCLE_4K_ERASE,
	HSFSTS_CYCLE_64K_ERASE,
	HSFSTS_CYCLE_RDSFDP,
	HSFSTS_CYCLE_RDID,
	HSFSTS_CYCLE_WR_STATUS,
	HSFSTS_CYCLE_RD_STATUS,
};

#define HSFSTS_FGO		BIT(16)
#define HSFSTS_FLOCKDN		BIT(15)
#define HSFSTS_FDV		BIT(14)
#define HSFSTS_FDOPSS		BIT(13)
#define HSFSTS_WRSDIS		BIT(11)
#define HSFSTS_SAF_CE		BIT(8)
#define HSFSTS_SAF_ACTIVE	BIT(7)
#define HSFSTS_SAF_LE		BIT(6)
#define HSFSTS_SCIP		BIT(5)
#define HSFSTS_SAF_DLE		BIT(4)
#define HSFSTS_SAF_ERROR	BIT(3)
#define HSFSTS_AEL		BIT(2)
#define HSFSTS_FCERR		BIT(1)
#define HSFSTS_FDONE		BIT(0)
#define HSFSTS_W1C_BITS		0xff

/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
#define SPIBAR_FDATA_FIFO_SIZE		0x40

#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS	5000

enum ich_version {
	ICHV_7,
	ICHV_9,
	ICHV_APL,
};

struct ich_spi_priv {
	int opmenu;
	int menubytes;
	void *base;		/* Base of register set */
	int preop;
	int optype;
	int addr;
	int data;
	unsigned databytes;
	int status;
	int control;
	int bbar;
	int bcr;
	uint32_t *pr;		/* only for ich9 */
	int speed;		/* pointer to speed control */
	ulong max_speed;	/* Maximum bus speed in MHz */
	ulong cur_speed;	/* Current bus speed */
	struct spi_trans trans;	/* current transaction in progress */
	struct udevice *pch;	/* PCH, used to control SPI access */
};

#endif /* _ICH_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
1853030e SG	2	/*
	3	* Copyright (c) 2011 The Chromium OS Authors.
	4	*
1853030e SG	5	* This file is derived from the flashrom project.
	6	*/
	7
9eb4339b BM	8	#ifndef _ICH_H_
	9	#define _ICH_H_
	10
cd93d625	11	#include <linux/bitops.h>
1853030e SG	12	struct ich7_spi_regs {
	13	uint16_t spis;
	14	uint16_t spic;
	15	uint32_t spia;
	16	uint64_t spid[8];
	17	uint64_t _pad;
	18	uint32_t bbar;
	19	uint16_t preop;
	20	uint16_t optype;
	21	uint8_t opmenu[8];
	22	} __packed;
	23
	24	struct ich9_spi_regs {
9eb4339b	25	uint32_t bfpr; /* 0x00 */
1853030e SG	26	uint16_t hsfs;
	27	uint16_t hsfc;
	28	uint32_t faddr;
	29	uint32_t _reserved0;
9eb4339b BM	30	uint32_t fdata[16]; /* 0x10 */
9eb4339b BM	31	uint32_t frap; /* 0x50 */
1853030e SG	32	uint32_t freg[5];
1853030e SG	33	uint32_t _reserved1[3];
9eb4339b	34	uint32_t pr[5]; /* 0x74 */
1853030e	35	uint32_t _reserved2[2];
9eb4339b	36	uint8_t ssfs; /* 0x90 */
1853030e	37	uint8_t ssfc[3];
9eb4339b	38	uint16_t preop; /* 0x94 */
1853030e	39	uint16_t optype;
9eb4339b	40	uint8_t opmenu[8]; /* 0x98 */
1853030e SG	41	uint32_t bbar;
1853030e SG	42	uint8_t _reserved3[12];
9eb4339b	43	uint32_t fdoc; /* 0xb0 */
1853030e SG	44	uint32_t fdod;
1853030e SG	45	uint8_t _reserved4[8];
9eb4339b	46	uint32_t afc; /* 0xc0 */
1853030e SG	47	uint32_t lvscc;
	48	uint32_t uvscc;
	49	uint8_t _reserved5[4];
9eb4339b	50	uint32_t fpb; /* 0xd0 */
1853030e	51	uint8_t _reserved6[28];
9eb4339b	52	uint32_t srdl; /* 0xf0 */
1853030e	53	uint32_t srdc;
5093badb SG	54	uint32_t scs;
5093badb SG	55	uint32_t bcr;
1853030e SG	56	} __packed;
	57
	58	enum {
	59	SPIS_SCIP = 0x0001,
	60	SPIS_GRANT = 0x0002,
	61	SPIS_CDS = 0x0004,
	62	SPIS_FCERR = 0x0008,
	63	SSFS_AEL = 0x0010,
	64	SPIS_LOCK = 0x8000,
	65	SPIS_RESERVED_MASK = 0x7ff0,
	66	SSFS_RESERVED_MASK = 0x7fe2
	67	};
	68
	69	enum {
	70	SPIC_SCGO = 0x000002,
	71	SPIC_ACS = 0x000004,
	72	SPIC_SPOP = 0x000008,
	73	SPIC_DBC = 0x003f00,
	74	SPIC_DS = 0x004000,
	75	SPIC_SME = 0x008000,
	76	SSFC_SCF_MASK = 0x070000,
	77	SSFC_RESERVED = 0xf80000,
	78
	79	/* Mask for speed byte, biuts 23:16 of SSFC */
	80	SSFC_SCF_33MHZ = 0x01,
	81	};
	82
	83	enum {
	84	HSFS_FDONE = 0x0001,
	85	HSFS_FCERR = 0x0002,
	86	HSFS_AEL = 0x0004,
	87	HSFS_BERASE_MASK = 0x0018,
	88	HSFS_BERASE_SHIFT = 3,
	89	HSFS_SCIP = 0x0020,
	90	HSFS_FDOPSS = 0x2000,
	91	HSFS_FDV = 0x4000,
	92	HSFS_FLOCKDN = 0x8000
	93	};
	94
	95	enum {
	96	HSFC_FGO = 0x0001,
	97	HSFC_FCYCLE_MASK = 0x0006,
	98	HSFC_FCYCLE_SHIFT = 1,
	99	HSFC_FDBC_MASK = 0x3f00,
	100	HSFC_FDBC_SHIFT = 8,
	101	HSFC_FSMIE = 0x8000
	102	};
	103
1853030e	104	struct spi_trans {
0709ddb6	105	uint8_t cmd;
1853030e SG	106	const uint8_t *out;
	107	uint32_t bytesout;
	108	uint8_t *in;
	109	uint32_t bytesin;
	110	uint8_t type;
	111	uint8_t opcode;
	112	uint32_t offset;
	113	};
	114
4759dffe SR	115	#define SPI_OPCODE_WRSR 0x01
	116	#define SPI_OPCODE_PAGE_PROGRAM 0x02
	117	#define SPI_OPCODE_READ 0x03
	118	#define SPI_OPCODE_WRDIS 0x04
	119	#define SPI_OPCODE_RDSR 0x05
9eb4339b BM	120	#define SPI_OPCODE_WREN 0x06
9eb4339b BM	121	#define SPI_OPCODE_FAST_READ 0x0b
4759dffe SR	122	#define SPI_OPCODE_ERASE_SECT 0x20
	123	#define SPI_OPCODE_READ_ID 0x9f
	124	#define SPI_OPCODE_ERASE_BLOCK 0xd8
	125
	126	#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
	127	#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
	128	#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
	129	#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
	130
	131	#define SPI_OPMENU_0 SPI_OPCODE_WRSR
	132	#define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
	133
	134	#define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM
	135	#define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
	136
	137	#define SPI_OPMENU_2 SPI_OPCODE_READ
	138	#define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
	139
	140	#define SPI_OPMENU_3 SPI_OPCODE_RDSR
	141	#define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS
	142
	143	#define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT
	144	#define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
	145
	146	#define SPI_OPMENU_5 SPI_OPCODE_READ_ID
	147	#define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS
	148
	149	#define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK
	150	#define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
	151
	152	#define SPI_OPMENU_7 SPI_OPCODE_FAST_READ
	153	#define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
	154
	155	#define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) \| SPI_OPCODE_WREN)
	156	#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) \| (SPI_OPTYPE_6 << 12) \| \
	157	(SPI_OPTYPE_5 << 10) \| (SPI_OPTYPE_4 << 8) \| \
	158	(SPI_OPTYPE_3 << 6) \| (SPI_OPTYPE_2 << 4) \| \
	159	(SPI_OPTYPE_1 << 2) \| (SPI_OPTYPE_0 << 0))
	160	#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) \| (SPI_OPMENU_6 << 16) \| \
	161	(SPI_OPMENU_5 << 8) \| (SPI_OPMENU_4 << 0))
	162	#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) \| (SPI_OPMENU_2 << 16) \| \
	163	(SPI_OPMENU_1 << 8) \| (SPI_OPMENU_0 << 0))
9eb4339b	164
0709ddb6 BM	165	#define ICH_BOUNDARY 0x1000
0709ddb6 BM	166
1facebd1 SG	167	#define HSFSTS_FDBC_SHIFT 24
	168	#define HSFSTS_FDBC_MASK (0x3f << HSFSTS_FDBC_SHIFT)
	169	#define HSFSTS_WET BIT(21)
	170	#define HSFSTS_FCYCLE_SHIFT 17
	171	#define HSFSTS_FCYCLE_MASK (0xf << HSFSTS_FCYCLE_SHIFT)
	172
	173	/* Supported flash cycle types */
	174	enum hsfsts_cycle_t {
	175	HSFSTS_CYCLE_READ = 0,
	176	HSFSTS_CYCLE_WRITE = 2,
	177	HSFSTS_CYCLE_4K_ERASE,
	178	HSFSTS_CYCLE_64K_ERASE,
	179	HSFSTS_CYCLE_RDSFDP,
	180	HSFSTS_CYCLE_RDID,
	181	HSFSTS_CYCLE_WR_STATUS,
	182	HSFSTS_CYCLE_RD_STATUS,
	183	};
	184
	185	#define HSFSTS_FGO BIT(16)
	186	#define HSFSTS_FLOCKDN BIT(15)
	187	#define HSFSTS_FDV BIT(14)
	188	#define HSFSTS_FDOPSS BIT(13)
	189	#define HSFSTS_WRSDIS BIT(11)
	190	#define HSFSTS_SAF_CE BIT(8)
	191	#define HSFSTS_SAF_ACTIVE BIT(7)
	192	#define HSFSTS_SAF_LE BIT(6)
	193	#define HSFSTS_SCIP BIT(5)
	194	#define HSFSTS_SAF_DLE BIT(4)
	195	#define HSFSTS_SAF_ERROR BIT(3)
	196	#define HSFSTS_AEL BIT(2)
	197	#define HSFSTS_FCERR BIT(1)
	198	#define HSFSTS_FDONE BIT(0)
	199	#define HSFSTS_W1C_BITS 0xff
	200
	201	/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
	202	#define SPIBAR_FDATA_FIFO_SIZE 0x40
	203
	204	#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000
	205
6e670b5c BM	206	enum ich_version {
	207	ICHV_7,
	208	ICHV_9,
3937df3d	209	ICHV_APL,
6e670b5c BM	210	};
6e670b5c BM	211
9eb4339b	212	struct ich_spi_priv {
9eb4339b BM	213	int opmenu;
	214	int menubytes;
	215	void base; / Base of register set */
	216	int preop;
	217	int optype;
	218	int addr;
	219	int data;
	220	unsigned databytes;
	221	int status;
	222	int control;
	223	int bbar;
	224	int bcr;
	225	uint32_t pr; / only for ich9 */
	226	int speed; /* pointer to speed control */
	227	ulong max_speed; /* Maximum bus speed in MHz */
	228	ulong cur_speed; /* Current bus speed */
1853030e	229	struct spi_trans trans; /* current transaction in progress */
17e75449	230	struct udevice pch; / PCH, used to control SPI access */
1853030e	231	};
9eb4339b BM	232
9eb4339b BM	233	#endif /* _ICH_H_ */