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powerpc: Remove unneccessary #ifdefs in reginfo
[u-boot.git] / arch / powerpc / cpu / mpc86xx / cpu.c
CommitLineData
debb7354 1/*
9ff32d8c 2 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
cb5965fb 3 * Jeff Brown
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4 * Srikanth Srinivasan ([email protected])
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8
9#include <common.h>
10#include <watchdog.h>
11#include <command.h>
12#include <asm/cache.h>
e34a0e91 13#include <asm/mmu.h>
debb7354 14#include <mpc86xx.h>
4f93f8b1 15#include <asm/fsl_law.h>
f3603b43 16#include <asm/ppc.h>
debb7354 17
0e870980
PA
18DECLARE_GLOBAL_DATA_PTR;
19
4ef630df
PT
20/*
21 * Default board reset function
22 */
23static void
24__board_reset(void)
25{
26 /* Do nothing */
27}
f9a109b3 28void board_reset(void) __attribute__((weak, alias("__board_reset")));
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PT
29
30
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31int
32checkcpu(void)
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33{
34 sys_info_t sysinfo;
35 uint pvr, svr;
debb7354 36 uint major, minor;
a1c8a719 37 char buf1[32], buf2[32];
6d0f6bcf 38 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
9553df86 39 volatile ccsr_gur_t *gur = &immap->im_gur;
480f6179 40 struct cpu_type *cpu;
a1c8a719 41 uint msscr0 = mfspr(MSSCR0);
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42
43 svr = get_svr();
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44 major = SVR_MAJ(svr);
45 minor = SVR_MIN(svr);
46
21170c80
PA
47 if (cpu_numcores() > 1) {
48#ifndef CONFIG_MP
49 puts("Unicore software on multiprocessor system!!\n"
50 "To enable mutlticore build define CONFIG_MP\n");
51#endif
52 }
a1c8a719
PT
53 puts("CPU: ");
54
67ac13b1 55 cpu = gd->arch.cpu;
0e870980 56
58442dc0 57 puts(cpu->name);
480f6179 58
debb7354 59 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
a1c8a719
PT
60 puts("Core: ");
61
62 pvr = get_pvr();
a1c8a719
PT
63 major = PVR_E600_MAJ(pvr);
64 minor = PVR_E600_MIN(pvr);
65
6770c5e2 66 printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
a1c8a719
PT
67 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
68 puts("\n Core1Translation Enabled");
69 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
70
71 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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72
73 get_sys_info(&sysinfo);
74
a1c8a719 75 puts("Clock Configuration:\n");
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76 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
77 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
a1c8a719 78 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
997399fa
PK
79 strmhz(buf1, sysinfo.freq_systembus / 2),
80 strmhz(buf2, sysinfo.freq_systembus));
5c9efb36 81
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PK
82 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
83 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
debb7354 84 } else {
a9f3acbc 85 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
997399fa 86 sysinfo.freq_localbus);
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87 }
88
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SK
89 puts("L1: D-cache 32 KiB enabled\n");
90 puts(" I-cache 32 KiB enabled\n");
a1c8a719
PT
91
92 puts("L2: ");
93 if (get_l2cr() & 0x80000000) {
1425a87b 94#if defined(CONFIG_ARCH_MPC8610)
a1c8a719 95 puts("256");
4f5554c6 96#elif defined(CONFIG_ARCH_MPC8641)
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PT
97 puts("512");
98#endif
6b44d9e5 99 puts(" KiB enabled\n");
a1c8a719 100 } else {
cb5965fb 101 puts("Disabled\n");
a1c8a719 102 }
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103
104 return 0;
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105}
106
107
c22a711d 108int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
debb7354 109{
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PT
110 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
111 volatile ccsr_gur_t *gur = &immap->im_gur;
5c9efb36 112
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113 /* Attempt board-specific reset */
114 board_reset();
5c9efb36 115
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116 /* Next try asserting HRESET_REQ */
117 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
5c9efb36 118
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119 while (1)
120 ;
c22a711d
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121
122 return 1;
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123}
124
125
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126/*
127 * Get timebase clock frequency
128 */
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129unsigned long
130get_tbclk(void)
debb7354 131{
ffff3ae5 132 sys_info_t sys_info;
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133
134 get_sys_info(&sys_info);
997399fa 135 return (sys_info.freq_systembus + 3L) / 4L;
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136}
137
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138
139#if defined(CONFIG_WATCHDOG)
140void
141watchdog_reset(void)
142{
1425a87b 143#if defined(CONFIG_ARCH_MPC8610)
3473ab73
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144 /*
145 * This actually feed the hard enabled watchdog.
146 */
6d0f6bcf 147 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
3473ab73
JJ
148 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
149 volatile ccsr_gur_t *gur = &immap->im_gur;
150 u32 tmp = gur->pordevsr;
151
152 if (tmp & 0x4000) {
153 wdt->swsrr = 0x556c;
154 wdt->swsrr = 0xaa39;
155 }
156#endif
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157}
158#endif /* CONFIG_WATCHDOG */
159
4f93f8b1
BB
160/*
161 * Print out the state of various machine registers.
e34a0e91 162 * Currently prints out LAWs, BR0/OR0, and BATs
4f93f8b1 163 */
f3603b43 164void print_reginfo(void)
4f93f8b1 165{
e34a0e91 166 print_bats();
4f93f8b1 167 print_laws();
f51cdaf1 168 print_lbc_regs();
debb7354 169}
9ff32d8c
TT
170
171/*
172 * Set the DDR BATs to reflect the actual size of DDR.
173 *
174 * dram_size is the actual size of DDR, in bytes
175 *
176 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
177 * are using a single BAT to cover DDR.
178 *
179 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
180 * is not defined) then we might have a situation where U-Boot will attempt
181 * to relocated itself outside of the region mapped by DBAT0.
182 * This will cause a machine check.
183 *
184 * Currently we are limited to power of two sized DDR since we only use a
185 * single bat. If a non-power of two size is used that is less than
186 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
187 *
188 */
189void setup_ddr_bat(phys_addr_t dram_size)
190{
191 unsigned long batu, bl;
192
193 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
194
195 if (BATU_SIZE(bl) != dram_size) {
196 u64 sz = (u64)dram_size - BATU_SIZE(bl);
197 print_size(sz, " left unmapped\n");
198 }
199
200 batu = bl | BATU_VS | BATU_VP;
201 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
202 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
203}
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