[u-boot.git] / include / configs / sequoia.h

/*
 * (C) Copyright 2006-2007
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2006
 * Jacqueline Pira-Ferriol, AMCC/IBM, [email protected]
 * Alain Saurel,            AMCC/IBM, [email protected]
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * sequoia.h - configuration for Sequoia & Rainier boards
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)	*/
#ifndef CONFIG_RAINIER
#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
#else
#define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
#endif
#define CONFIG_440		1		/* ... PPC440 family	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
/* Detect Sequoia PLL input clock automatically via CPLD bit		*/
#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
				33333333 : 33000000)

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

#define CFG_BOOT_BASE_ADDR	0xf0000000
#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000

/* Don't change either of these */
#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/

#define CFG_USB2D0_BASE		0xe0000100
#define CFG_USB_DEVICE		0xe0000000
#define CFG_USB_HOST		0xe0000400
#define CFG_BCSR_BASE		0xc0000000

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer
 *----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
#define CFG_INIT_RAM_END	(4 << 10)
#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
#define CONFIG_BAUDRATE		115200
#define CONFIG_SERIAL_MULTI     1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE

#define CFG_BAUDRATE_TABLE						\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
#define CFG_ENV_IS_EMBEDDED	1	/* use embedded environment */
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif

/*
 * IPL (Initial Program Loader, integrated inside CPU)
 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 *
 * SPL (Secondary Program Loader)
 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 * controller and the NAND controller so that the special U-Boot image can be
 * loaded from NAND to SDRAM.
 *
 * NUB (NAND U-Boot)
 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 *
 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 * set up. While still running from cache, I experienced problems accessing
 * the NAND controller.	sr - 2006-08-25
 */
#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here	*/
#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)

/*
 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 */
#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/

/*
 * Now the NAND chip has to be defined (no autodetection used!)
 */
#define CFG_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
#define CFG_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
#define CFG_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
#undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/

#define CFG_NAND_ECCSIZE	256
#define CFG_NAND_ECCBYTES	3
#define CFG_NAND_ECCSTEPS	(CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
#define CFG_NAND_OOBSIZE	16
#define CFG_NAND_ECCTOTAL	(CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
#define CFG_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}

#ifdef CFG_ENV_IS_IN_NAND
/*
 * For NAND booting the environment is embedded in the U-Boot image. Please take
 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 */
#define CFG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE			/* use DDR2 optimization	*/
#endif

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
#define CFG_DTT_MAX_TEMP	70
#define CFG_DTT_LOW_TEMP	-30
#define CFG_DTT_HYSTERESIS	3

#define CONFIG_PREBOOT	"echo;"						\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

/* Setup some board specific values for the default environment variables */
#ifndef CONFIG_RAINIER
#define CONFIG_HOSTNAME		sequoia
#define CFG_BOOTFILE		"bootfile=/tftpboot/sequoia/uImage\0"
#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_HOSTNAME		rainier
#define CFG_BOOTFILE		"bootfile=/tftpboot/rainier/uImage\0"
#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CFG_BOOTFILE							\
	CFG_ROOTPATH							\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"kernel_addr=FC000000\0"					\
	"ramdisk_addr=FC180000\0"					\
	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
		"cp.b 200000 FFFA0000 60000\0"			        \
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_M88E1111_PHY	1
#define	CONFIG_IBM_EMAC4_V4	1
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/

#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NET_MULTI	1
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY1_ADDR	1

/* USB */
#ifdef CONFIG_440EPX
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE

#define CMD_USB			CFG_CMD_USB
#else
#define CMD_USB			0	/* no USB on 440GRx		*/
#endif /* CONFIG_440EPX */

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define CONFIG_COMMANDS       (CONFIG_CMD_DFL	|	\
			       CFG_CMD_ASKENV	|	\
			       CFG_CMD_DHCP	|	\
			       CFG_CMD_DTT	|	\
			       CFG_CMD_DIAG	|	\
			       CFG_CMD_EEPROM	|	\
			       CFG_CMD_ELF	|	\
			       CFG_CMD_FAT	|	\
			       CFG_CMD_I2C	|	\
			       CFG_CMD_IRQ	|	\
			       CFG_CMD_MII	|	\
			       CFG_CMD_NAND	|	\
			       CFG_CMD_NET	|	\
			       CFG_CMD_NFS	|	\
			       CFG_CMD_PCI	|	\
			       CFG_CMD_PING	|	\
			       CFG_CMD_REGINFO	|	\
			       CFG_CMD_SDRAM	|	\
			       CMD_USB)

#define CONFIG_SUPPORT_VFAT

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	        16	/* max number of command args	*/
#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/

/*
 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
/* Memory Bank 0 (NOR-FLASH) initialization					*/
#define CFG_EBC_PB0AP		0x03017200
#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)

/* Memory Bank 3 (NAND-FLASH) initialization					*/
#define CFG_EBC_PB3AP		0x018003c0
#define CFG_EBC_PB3CR		(CFG_NAND_ADDR | 0x1c000)
#else
#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
/* Memory Bank 3 (NOR-FLASH) initialization					*/
#define CFG_EBC_PB3AP		0x03017200
#define CFG_EBC_PB3CR		(CFG_FLASH_BASE | 0xda000)

/* Memory Bank 0 (NAND-FLASH) initialization					*/
#define CFG_EBC_PB0AP		0x018003c0
#define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1c000)
#endif

/* Memory Bank 2 (CPLD) initialization						*/
#define CFG_EBC_PB2AP		0x24814580
#define CFG_EBC_PB2CR		(CFG_BCSR_BASE | 0x38000)

/*-----------------------------------------------------------------------
 * NAND FLASH
 *----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS		1
#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 *----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	      /* ...			            */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
887e2ec9	1	/*
e802594b	2	* (C) Copyright 2006-2007
887e2ec9 SR	3	* Stefan Roese, DENX Software Engineering, [email protected].
	4	*
	5	* (C) Copyright 2006
	6	* Jacqueline Pira-Ferriol, AMCC/IBM, [email protected]
	7	* Alain Saurel, AMCC/IBM, [email protected]
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/************************************************************************
e802594b	26	* sequoia.h - configuration for Sequoia & Rainier boards
887e2ec9 SR	27	***********************************************************************/
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
e802594b	34	/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
854bc8da	35	#ifndef CONFIG_RAINIER
887e2ec9	36	#define CONFIG_440EPX 1 /* Specific PPC440EPx */
854bc8da SR	37	#else
	38	#define CONFIG_440GRX 1 /* Specific PPC440GRx */
	39	#endif
efa35cf1	40	#define CONFIG_440 1 /* ... PPC440 family */
887e2ec9	41	#define CONFIG_4xx 1 /* ... PPC4xx family */
e3b8c78b JM	42	/* Detect Sequoia PLL input clock automatically via CPLD bit */
e3b8c78b JM	43	#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
193b4a3b	44	33333333 : 33000000)
887e2ec9 SR	45
	46	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	47	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	48
	49	/*-----------------------------------------------------------------------
	50	* Base addresses -- Note these are effective addresses where the
	51	* actual resources get mapped (not physical addresses)
	52	----------------------------------------------------------------------/
	53	#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
	54	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	55
	56	#define CFG_BOOT_BASE_ADDR 0xf0000000
	57	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
4ef62514	58	#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
887e2ec9 SR	59	#define CFG_MONITOR_BASE TEXT_BASE
	60	#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
	61	#define CFG_OCM_BASE 0xe0010000 /* ocm */
	62	#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
	63	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	64	#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
	65	#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
	66	#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
	67
	68	/* Don't change either of these */
	69	#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
	70
	71	#define CFG_USB2D0_BASE 0xe0000100
	72	#define CFG_USB_DEVICE 0xe0000000
	73	#define CFG_USB_HOST 0xe0000400
	74	#define CFG_BCSR_BASE 0xc0000000
	75
	76	/*-----------------------------------------------------------------------
	77	* Initial RAM & stack pointer
	78	----------------------------------------------------------------------/
887e2ec9	79	/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
887e2ec9	80	#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
887e2ec9 SR	81	#define CFG_INIT_RAM_END (4 << 10)
	82	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
	83	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	84	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	85
	86	/*-----------------------------------------------------------------------
	87	* Serial Port
	88	----------------------------------------------------------------------/
	89	#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
	90	#define CONFIG_BAUDRATE 115200
	91	#define CONFIG_SERIAL_MULTI 1
	92	/* define this if you want console on UART1 */
	93	#undef CONFIG_UART1_CONSOLE
	94
	95	#define CFG_BAUDRATE_TABLE \
	96	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	97
	98	/*-----------------------------------------------------------------------
	99	* Environment
	100	----------------------------------------------------------------------/
d12ae808	101	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
887e2ec9 SR	102	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	103	#else
	104	#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
d1a72545	105	#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
887e2ec9	106	#endif
887e2ec9 SR	107
	108	/*-----------------------------------------------------------------------
	109	* FLASH related
	110	----------------------------------------------------------------------/
	111	#define CFG_FLASH_CFI /* The flash is CFI compatible */
	112	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
	113
	114	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
	115
	116	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	117	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	118
	119	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	120	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	121
	122	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	123	#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
	124
	125	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	126	#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
	127
	128	#ifdef CFG_ENV_IS_IN_FLASH
	129	#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	130	#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
	131	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	132
	133	/* Address and size of Redundant Environment Sector */
	134	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	135	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	136	#endif
	137
887e2ec9 SR	138	/*
	139	* IPL (Initial Program Loader, integrated inside CPU)
	140	* Will load first 4k from NAND (SPL) into cache and execute it from there.
	141	*
	142	* SPL (Secondary Program Loader)
	143	* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
	144	* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
	145	* controller and the NAND controller so that the special U-Boot image can be
	146	* loaded from NAND to SDRAM.
	147	*
	148	* NUB (NAND U-Boot)
	149	* This NAND U-Boot (NUB) is a special U-Boot version which can be started
	150	* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
	151	*
	152	* On 440EPx the SPL is copied to SDRAM before the NAND controller is
	153	* set up. While still running from cache, I experienced problems accessing
	154	* the NAND controller. sr - 2006-08-25
	155	*/
	156	#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
	157	#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
	158	#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
	159	#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
	160	#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
	161	#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
	162
	163	/*
	164	* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
	165	*/
	166	#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
	167	#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
	168
	169	/*
	170	* Now the NAND chip has to be defined (no autodetection used!)
	171	*/
9d909604	172	#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
887e2ec9	173	#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
9d909604 SR	174	#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
9d909604 SR	175	#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
887e2ec9 SR	176	#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
887e2ec9 SR	177
9d909604 SR	178	#define CFG_NAND_ECCSIZE 256
	179	#define CFG_NAND_ECCBYTES 3
	180	#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
	181	#define CFG_NAND_OOBSIZE 16
	182	#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
	183	#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
	184
887e2ec9	185	#ifdef CFG_ENV_IS_IN_NAND
d12ae808 SR	186	/*
	187	* For NAND booting the environment is embedded in the U-Boot image. Please take
	188	* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
	189	*/
	190	#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
	191	#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
887e2ec9 SR	192	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
	193	#endif
	194
	195	/*-----------------------------------------------------------------------
	196	* DDR SDRAM
	197	----------------------------------------------------------------------/
02388983 SR	198	#define CFG_MBYTES_SDRAM (256) /* 256MB */
	199	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	200	#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
	201	#endif
887e2ec9 SR	202
	203	/*-----------------------------------------------------------------------
	204	* I2C
	205	----------------------------------------------------------------------/
	206	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	207	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	208	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	209	#define CFG_I2C_SLAVE 0x7F
	210
	211	#define CFG_I2C_MULTI_EEPROMS
	212	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
	213	#define CFG_I2C_EEPROM_ADDR_LEN 1
	214	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	215	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	216	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	217
887e2ec9 SR	218	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	219	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	220	#define CONFIG_DTT_AD7414 1 /* use AD7414 */
	221	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
	222	#define CFG_DTT_MAX_TEMP 70
	223	#define CFG_DTT_LOW_TEMP -30
	224	#define CFG_DTT_HYSTERESIS 3
	225
	226	#define CONFIG_PREBOOT "echo;" \
	227	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	228	"echo"
	229
	230	#undef CONFIG_BOOTARGS
	231
e802594b SR	232	/* Setup some board specific values for the default environment variables */
	233	#ifndef CONFIG_RAINIER
	234	#define CONFIG_HOSTNAME sequoia
	235	#define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0"
	236	#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
	237	#else
	238	#define CONFIG_HOSTNAME rainier
	239	#define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0"
	240	#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
	241	#endif
	242
887e2ec9	243	#define CONFIG_EXTRA_ENV_SETTINGS \
e802594b SR	244	CFG_BOOTFILE \
e802594b SR	245	CFG_ROOTPATH \
887e2ec9	246	"netdev=eth0\0" \
887e2ec9 SR	247	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	248	"nfsroot=${serverip}:${rootpath}\0" \
	249	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	250	"addip=setenv bootargs ${bootargs} " \
	251	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	252	":${hostname}:${netdev}:off panic=1\0" \
	253	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	254	"flash_nfs=run nfsargs addip addtty;" \
	255	"bootm ${kernel_addr}\0" \
	256	"flash_self=run ramargs addip addtty;" \
	257	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	258	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	259	"bootm\0" \
4ef62514 SR	260	"kernel_addr=FC000000\0" \
4ef62514 SR	261	"ramdisk_addr=FC180000\0" \
e802594b	262	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
887e2ec9	263	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
e802594b	264	"cp.b 200000 FFFA0000 60000\0" \
887e2ec9 SR	265	"upd=run load;run update\0" \
	266	""
	267	#define CONFIG_BOOTCOMMAND "run flash_self"
	268
	269	#if 0
	270	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	271	#else
	272	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	273	#endif
	274
	275	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	276	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	277
	278	#define CONFIG_M88E1111_PHY 1
	279	#define CONFIG_IBM_EMAC4_V4 1
	280	#define CONFIG_MII 1 /* MII PHY management */
	281	#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
	282
	283	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
	284	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	285
	286	#define CONFIG_HAS_ETH0
	287	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
	288
	289	#define CONFIG_NET_MULTI 1
	290	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
	291	#define CONFIG_PHY1_ADDR 1
	292
	293	/* USB */
854bc8da	294	#ifdef CONFIG_440EPX
887e2ec9 SR	295	#define CONFIG_USB_OHCI
	296	#define CONFIG_USB_STORAGE
	297
	298	/* Comment this out to enable USB 1.1 device */
	299	#define USB_2_0_DEVICE
	300
854bc8da SR	301	#define CMD_USB CFG_CMD_USB
	302	#else
	303	#define CMD_USB 0 /* no USB on 440GRx */
	304	#endif /* CONFIG_440EPX */
	305
887e2ec9 SR	306	/* Partitions */
	307	#define CONFIG_MAC_PARTITION
	308	#define CONFIG_DOS_PARTITION
	309	#define CONFIG_ISO_PARTITION
	310
	311	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	312	CFG_CMD_ASKENV \| \
	313	CFG_CMD_DHCP \| \
	314	CFG_CMD_DTT \| \
	315	CFG_CMD_DIAG \| \
	316	CFG_CMD_EEPROM \| \
	317	CFG_CMD_ELF \| \
	318	CFG_CMD_FAT \| \
	319	CFG_CMD_I2C \| \
	320	CFG_CMD_IRQ \| \
	321	CFG_CMD_MII \| \
	322	CFG_CMD_NAND \| \
	323	CFG_CMD_NET \| \
	324	CFG_CMD_NFS \| \
	325	CFG_CMD_PCI \| \
	326	CFG_CMD_PING \| \
	327	CFG_CMD_REGINFO \| \
	328	CFG_CMD_SDRAM \| \
854bc8da	329	CMD_USB)
887e2ec9 SR	330
	331	#define CONFIG_SUPPORT_VFAT
	332
	333	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	334	#include <cmd_confdefs.h>
	335
	336	/*-----------------------------------------------------------------------
	337	* Miscellaneous configurable options
	338	----------------------------------------------------------------------/
	339	#define CFG_LONGHELP /* undef to save memory */
	340	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	341	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	342	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	343	#else
	344	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	345	#endif
	346	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	347	#define CFG_MAXARGS 16 /* max number of command args */
	348	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	349
	350	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	351	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	352
	353	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	354	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	355
	356	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	357
	358	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	359	#define CONFIG_LOOPW 1 /* enable loopw command */
	360	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	361	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	362	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	363
	364	/*-----------------------------------------------------------------------
	365	* PCI stuff
	366	----------------------------------------------------------------------/
	367	/* General PCI */
	368	#define CONFIG_PCI /* include pci support */
23744d6b	369	#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
887e2ec9 SR	370	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	371	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
	372
	373	/* Board-specific PCI */
	374	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
	375	#define CFG_PCI_TARGET_INIT
	376	#define CFG_PCI_MASTER_INIT
	377
	378	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
	379	#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
	380
	381	/*
	382	* For booting Linux, the board info and command line data
	383	* have to be in the first 8 MB of memory, since this is
	384	* the maximum mapped by the Linux kernel during initialization.
	385	*/
	386	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	387
	388	/*-----------------------------------------------------------------------
	389	* External Bus Controller (EBC) Setup
	390	----------------------------------------------------------------------/
887e2ec9 SR	391
	392	/*
	393	* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
	394	*/
	395	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	396	#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
	397	/* Memory Bank 0 (NOR-FLASH) initialization */
4be23a12	398	#define CFG_EBC_PB0AP 0x03017200
2db63365	399	#define CFG_EBC_PB0CR (CFG_FLASH_BASE \| 0xda000)
887e2ec9 SR	400
	401	/* Memory Bank 3 (NAND-FLASH) initialization */
	402	#define CFG_EBC_PB3AP 0x018003c0
2db63365	403	#define CFG_EBC_PB3CR (CFG_NAND_ADDR \| 0x1c000)
887e2ec9 SR	404	#else
	405	#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
	406	/* Memory Bank 3 (NOR-FLASH) initialization */
4be23a12	407	#define CFG_EBC_PB3AP 0x03017200
2db63365	408	#define CFG_EBC_PB3CR (CFG_FLASH_BASE \| 0xda000)
887e2ec9 SR	409
	410	/* Memory Bank 0 (NAND-FLASH) initialization */
	411	#define CFG_EBC_PB0AP 0x018003c0
2db63365	412	#define CFG_EBC_PB0CR (CFG_NAND_ADDR \| 0x1c000)
887e2ec9 SR	413	#endif
	414
	415	/* Memory Bank 2 (CPLD) initialization */
	416	#define CFG_EBC_PB2AP 0x24814580
2db63365	417	#define CFG_EBC_PB2CR (CFG_BCSR_BASE \| 0x38000)
887e2ec9	418
43a2b0e7 SR	419	/*-----------------------------------------------------------------------
	420	* NAND FLASH
	421	----------------------------------------------------------------------/
	422	#define CFG_MAX_NAND_DEVICE 1
	423	#define NAND_MAX_CHIPS 1
	424	#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
	425	#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
	426
887e2ec9 SR	427	/*-----------------------------------------------------------------------
	428	* Cache Configuration
	429	----------------------------------------------------------------------/
	430	#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
	431	#define CFG_CACHELINE_SIZE 32 /* ... */
	432	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	433	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	434	#endif
	435
	436	/*
	437	* Internal Definitions
	438	*
	439	* Boot Flags
	440	*/
	441	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	442	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	443
	444	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	445	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	446	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	447	#endif
	448	#endif /* __CONFIG_H */