[u-boot.git] / drivers / usb / eth / asix.c

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <usb.h>
#include <linux/mii.h>
#include "usb_ether.h"
#include <malloc.h>


/* ASIX AX8817X based USB 2.0 Ethernet Devices */

#define AX_CMD_SET_SW_MII		0x06
#define AX_CMD_READ_MII_REG		0x07
#define AX_CMD_WRITE_MII_REG		0x08
#define AX_CMD_SET_HW_MII		0x0a
#define AX_CMD_READ_EEPROM		0x0b
#define AX_CMD_READ_RX_CTL		0x0f
#define AX_CMD_WRITE_RX_CTL		0x10
#define AX_CMD_WRITE_IPG0		0x12
#define AX_CMD_READ_NODE_ID		0x13
#define AX_CMD_WRITE_NODE_ID	0x14
#define AX_CMD_READ_PHY_ID		0x19
#define AX_CMD_WRITE_MEDIUM_MODE	0x1b
#define AX_CMD_WRITE_GPIOS		0x1f
#define AX_CMD_SW_RESET			0x20
#define AX_CMD_SW_PHY_SELECT		0x22

#define AX_SWRESET_CLEAR		0x00
#define AX_SWRESET_PRTE			0x04
#define AX_SWRESET_PRL			0x08
#define AX_SWRESET_IPRL			0x20
#define AX_SWRESET_IPPD			0x40

#define AX88772_IPG0_DEFAULT		0x15
#define AX88772_IPG1_DEFAULT		0x0c
#define AX88772_IPG2_DEFAULT		0x12

/* AX88772 & AX88178 Medium Mode Register */
#define AX_MEDIUM_PF		0x0080
#define AX_MEDIUM_JFE		0x0040
#define AX_MEDIUM_TFC		0x0020
#define AX_MEDIUM_RFC		0x0010
#define AX_MEDIUM_ENCK		0x0008
#define AX_MEDIUM_AC		0x0004
#define AX_MEDIUM_FD		0x0002
#define AX_MEDIUM_GM		0x0001
#define AX_MEDIUM_SM		0x1000
#define AX_MEDIUM_SBP		0x0800
#define AX_MEDIUM_PS		0x0200
#define AX_MEDIUM_RE		0x0100

#define AX88178_MEDIUM_DEFAULT	\
	(AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
	 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
	 AX_MEDIUM_RE)

#define AX88772_MEDIUM_DEFAULT	\
	(AX_MEDIUM_FD | AX_MEDIUM_RFC | \
	 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
	 AX_MEDIUM_AC | AX_MEDIUM_RE)

/* AX88772 & AX88178 RX_CTL values */
#define AX_RX_CTL_SO			0x0080
#define AX_RX_CTL_AB			0x0008

#define AX_DEFAULT_RX_CTL	\
	(AX_RX_CTL_SO | AX_RX_CTL_AB)

/* GPIO 2 toggles */
#define AX_GPIO_GPO2EN		0x10	/* GPIO2 Output enable */
#define AX_GPIO_GPO_2		0x20	/* GPIO2 Output value */
#define AX_GPIO_RSE		0x80	/* Reload serial EEPROM */

/* local defines */
#define ASIX_BASE_NAME "asx"
#define USB_CTRL_SET_TIMEOUT 5000
#define USB_CTRL_GET_TIMEOUT 5000
#define USB_BULK_SEND_TIMEOUT 5000
#define USB_BULK_RECV_TIMEOUT 5000

#define AX_RX_URB_SIZE 2048
#define PHY_CONNECT_TIMEOUT 5000

/* asix_flags defines */
#define FLAG_NONE			0
#define FLAG_TYPE_AX88172	(1U << 0)
#define FLAG_TYPE_AX88772	(1U << 1)
#define FLAG_TYPE_AX88772B	(1U << 2)
#define FLAG_EEPROM_MAC		(1U << 3) /* initial mac address in eeprom */

/* local vars */
static int curr_eth_dev; /* index for name of next device detected */

/* driver private */
struct asix_private {
	int flags;
};

/*
 * Asix infrastructure commands
 */
static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
			     u16 size, void *data)
{
	int len;

	debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
		"size=%d\n", cmd, value, index, size);

	len = usb_control_msg(
		dev->pusb_dev,
		usb_sndctrlpipe(dev->pusb_dev, 0),
		cmd,
		USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
		value,
		index,
		data,
		size,
		USB_CTRL_SET_TIMEOUT);

	return len == size ? 0 : -1;
}

static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
			    u16 size, void *data)
{
	int len;

	debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
		cmd, value, index, size);

	len = usb_control_msg(
		dev->pusb_dev,
		usb_rcvctrlpipe(dev->pusb_dev, 0),
		cmd,
		USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
		value,
		index,
		data,
		size,
		USB_CTRL_GET_TIMEOUT);
	return len == size ? 0 : -1;
}

static inline int asix_set_sw_mii(struct ueth_data *dev)
{
	int ret;

	ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
	if (ret < 0)
		debug("Failed to enable software MII access\n");
	return ret;
}

static inline int asix_set_hw_mii(struct ueth_data *dev)
{
	int ret;

	ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
	if (ret < 0)
		debug("Failed to enable hardware MII access\n");
	return ret;
}

static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
{
	ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);

	asix_set_sw_mii(dev);
	asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
	asix_set_hw_mii(dev);

	debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
			phy_id, loc, le16_to_cpu(*res));

	return le16_to_cpu(*res);
}

static void
asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
{
	ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
	*res = cpu_to_le16(val);

	debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
			phy_id, loc, val);
	asix_set_sw_mii(dev);
	asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
	asix_set_hw_mii(dev);
}

/*
 * Asix "high level" commands
 */
static int asix_sw_reset(struct ueth_data *dev, u8 flags)
{
	int ret;

	ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
	if (ret < 0)
		debug("Failed to send software reset: %02x\n", ret);
	else
		udelay(150 * 1000);

	return ret;
}

static inline int asix_get_phy_addr(struct ueth_data *dev)
{
	ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);

	int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);

	debug("asix_get_phy_addr()\n");

	if (ret < 0) {
		debug("Error reading PHYID register: %02x\n", ret);
		goto out;
	}
	debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
	ret = buf[1];

out:
	return ret;
}

static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
{
	int ret;

	debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
	ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
			0, 0, NULL);
	if (ret < 0) {
		debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
			mode, ret);
	}
	return ret;
}

static u16 asix_read_rx_ctl(struct ueth_data *dev)
{
	ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);

	int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);

	if (ret < 0)
		debug("Error reading RX_CTL register: %02x\n", ret);
	else
		ret = le16_to_cpu(*v);
	return ret;
}

static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
{
	int ret;

	debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
	ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
	if (ret < 0) {
		debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
				mode, ret);
	}
	return ret;
}

static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
{
	int ret;

	debug("asix_write_gpio() - value = 0x%04x\n", value);
	ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
	if (ret < 0) {
		debug("Failed to write GPIO value 0x%04x: %02x\n",
			value, ret);
	}
	if (sleep)
		udelay(sleep * 1000);

	return ret;
}

static int asix_write_hwaddr(struct eth_device *eth)
{
	struct ueth_data *dev = (struct ueth_data *)eth->priv;
	int ret;
	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);

	memcpy(buf, eth->enetaddr, ETH_ALEN);

	ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
	if (ret < 0)
		debug("Failed to set MAC address: %02x\n", ret);

	return ret;
}

/*
 * mii commands
 */

/*
 * mii_nway_restart - restart NWay (autonegotiation) for this interface
 *
 * Returns 0 on success, negative on error.
 */
static int mii_nway_restart(struct ueth_data *dev)
{
	int bmcr;
	int r = -1;

	/* if autoneg is off, it's an error */
	bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);

	if (bmcr & BMCR_ANENABLE) {
		bmcr |= BMCR_ANRESTART;
		asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
		r = 0;
	}

	return r;
}

static int asix_read_mac(struct eth_device *eth)
{
	struct ueth_data *dev = (struct ueth_data *)eth->priv;
	struct asix_private *priv = (struct asix_private *)dev->dev_priv;
	int i;
	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);

	if (priv->flags & FLAG_EEPROM_MAC) {
		for (i = 0; i < (ETH_ALEN >> 1); i++) {
			if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
					  0x04 + i, 0, 2, buf) < 0) {
				debug("Failed to read SROM address 04h.\n");
				return -1;
			}
			memcpy((eth->enetaddr + i * 2), buf, 2);
		}
	} else {
		if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
		     < 0) {
			debug("Failed to read MAC address.\n");
			return -1;
		}
		memcpy(eth->enetaddr, buf, ETH_ALEN);
	}

	return 0;
}

static int asix_basic_reset(struct ueth_data *dev)
{
	int embd_phy;
	u16 rx_ctl;

	if (asix_write_gpio(dev,
			AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
		return -1;

	/* 0x10 is the phy id of the embedded 10/100 ethernet phy */
	embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
	if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
				embd_phy, 0, 0, NULL) < 0) {
		debug("Select PHY #1 failed\n");
		return -1;
	}

	if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
		return -1;

	if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
		return -1;

	if (embd_phy) {
		if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
			return -1;
	} else {
		if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
			return -1;
	}

	rx_ctl = asix_read_rx_ctl(dev);
	debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
	if (asix_write_rx_ctl(dev, 0x0000) < 0)
		return -1;

	rx_ctl = asix_read_rx_ctl(dev);
	debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);

	return 0;
}

/*
 * Asix callbacks
 */
static int asix_init(struct eth_device *eth, bd_t *bd)
{
	struct ueth_data	*dev = (struct ueth_data *)eth->priv;
	int timeout = 0;
#define TIMEOUT_RESOLUTION 50	/* ms */
	int link_detected;

	debug("** %s()\n", __func__);

	dev->phy_id = asix_get_phy_addr(dev);
	if (dev->phy_id < 0)
		debug("Failed to read phy id\n");

	if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0)
		goto out_err;

	if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0)
		goto out_err;

	asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
	asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
			ADVERTISE_ALL | ADVERTISE_CSMA);
	mii_nway_restart(dev);

	if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
		goto out_err;

	if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
				AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
				AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
		debug("Write IPG,IPG1,IPG2 failed\n");
		goto out_err;
	}

	if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
		goto out_err;

	do {
		link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
			BMSR_LSTATUS;
		if (!link_detected) {
			if (timeout == 0)
				printf("Waiting for Ethernet connection... ");
			udelay(TIMEOUT_RESOLUTION * 1000);
			timeout += TIMEOUT_RESOLUTION;
		}
	} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
	if (link_detected) {
		if (timeout != 0)
			printf("done.\n");
	} else {
		printf("unable to connect.\n");
		goto out_err;
	}

	return 0;
out_err:
	return -1;
}

static int asix_send(struct eth_device *eth, void *packet, int length)
{
	struct ueth_data *dev = (struct ueth_data *)eth->priv;
	int err;
	u32 packet_len;
	int actual_len;
	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
		PKTSIZE + sizeof(packet_len));

	debug("** %s(), len %d\n", __func__, length);

	packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
	cpu_to_le32s(&packet_len);

	memcpy(msg, &packet_len, sizeof(packet_len));
	memcpy(msg + sizeof(packet_len), (void *)packet, length);
	if (length & 1)
		length++;

	err = usb_bulk_msg(dev->pusb_dev,
				usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
				(void *)msg,
				length + sizeof(packet_len),
				&actual_len,
				USB_BULK_SEND_TIMEOUT);
	debug("Tx: len = %u, actual = %u, err = %d\n",
			length + sizeof(packet_len), actual_len, err);

	return err;
}

static int asix_recv(struct eth_device *eth)
{
	struct ueth_data *dev = (struct ueth_data *)eth->priv;
	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
	unsigned char *buf_ptr;
	int err;
	int actual_len;
	u32 packet_len;

	debug("** %s()\n", __func__);

	err = usb_bulk_msg(dev->pusb_dev,
				usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
				(void *)recv_buf,
				AX_RX_URB_SIZE,
				&actual_len,
				USB_BULK_RECV_TIMEOUT);
	debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
		actual_len, err);
	if (err != 0) {
		debug("Rx: failed to receive\n");
		return -1;
	}
	if (actual_len > AX_RX_URB_SIZE) {
		debug("Rx: received too many bytes %d\n", actual_len);
		return -1;
	}

	buf_ptr = recv_buf;
	while (actual_len > 0) {
		/*
		 * 1st 4 bytes contain the length of the actual data as two
		 * complementary 16-bit words. Extract the length of the data.
		 */
		if (actual_len < sizeof(packet_len)) {
			debug("Rx: incomplete packet length\n");
			return -1;
		}
		memcpy(&packet_len, buf_ptr, sizeof(packet_len));
		le32_to_cpus(&packet_len);
		if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
			debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
			      packet_len, (~packet_len >> 16) & 0x7ff,
			      packet_len & 0x7ff);
			return -1;
		}
		packet_len = packet_len & 0x7ff;
		if (packet_len > actual_len - sizeof(packet_len)) {
			debug("Rx: too large packet: %d\n", packet_len);
			return -1;
		}

		/* Notify net stack */
		NetReceive(buf_ptr + sizeof(packet_len), packet_len);

		/* Adjust for next iteration. Packets are padded to 16-bits */
		if (packet_len & 1)
			packet_len++;
		actual_len -= sizeof(packet_len) + packet_len;
		buf_ptr += sizeof(packet_len) + packet_len;
	}

	return err;
}

static void asix_halt(struct eth_device *eth)
{
	debug("** %s()\n", __func__);
}

/*
 * Asix probing functions
 */
void asix_eth_before_probe(void)
{
	curr_eth_dev = 0;
}

struct asix_dongle {
	unsigned short vendor;
	unsigned short product;
	int flags;
};

static const struct asix_dongle const asix_dongles[] = {
	{ 0x05ac, 0x1402, FLAG_TYPE_AX88772 },	/* Apple USB Ethernet Adapter */
	{ 0x07d1, 0x3c05, FLAG_TYPE_AX88772 },	/* D-Link DUB-E100 H/W Ver B1 */
	/* Cables-to-Go USB Ethernet Adapter */
	{ 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
	{ 0x0b95, 0x7720, FLAG_TYPE_AX88772 },	/* Trendnet TU2-ET100 V3.0R */
	{ 0x0b95, 0x1720, FLAG_TYPE_AX88172 },	/* SMC */
	{ 0x0db0, 0xa877, FLAG_TYPE_AX88772 },	/* MSI - ASIX 88772a */
	{ 0x13b1, 0x0018, FLAG_TYPE_AX88172 },	/* Linksys 200M v2.1 */
	{ 0x1557, 0x7720, FLAG_TYPE_AX88772 },	/* 0Q0 cable ethernet */
	/* DLink DUB-E100 H/W Ver B1 Alternate */
	{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
	/* ASIX 88772B */
	{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
	{ 0x0000, 0x0000, FLAG_NONE }	/* END - Do not remove */
};

/* Probe to see if a new device is actually an asix device */
int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
		      struct ueth_data *ss)
{
	struct usb_interface *iface;
	struct usb_interface_descriptor *iface_desc;
	int ep_in_found = 0, ep_out_found = 0;
	int i;

	/* let's examine the device now */
	iface = &dev->config.if_desc[ifnum];
	iface_desc = &dev->config.if_desc[ifnum].desc;

	for (i = 0; asix_dongles[i].vendor != 0; i++) {
		if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
		    dev->descriptor.idProduct == asix_dongles[i].product)
			/* Found a supported dongle */
			break;
	}

	if (asix_dongles[i].vendor == 0)
		return 0;

	memset(ss, 0, sizeof(struct ueth_data));

	/* At this point, we know we've got a live one */
	debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
	      dev->descriptor.idVendor, dev->descriptor.idProduct);

	/* Initialize the ueth_data structure with some useful info */
	ss->ifnum = ifnum;
	ss->pusb_dev = dev;
	ss->subclass = iface_desc->bInterfaceSubClass;
	ss->protocol = iface_desc->bInterfaceProtocol;

	/* alloc driver private */
	ss->dev_priv = calloc(1, sizeof(struct asix_private));
	if (!ss->dev_priv)
		return 0;

	((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;

	/*
	 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
	 * int. We will ignore any others.
	 */
	for (i = 0; i < iface_desc->bNumEndpoints; i++) {
		/* is it an BULK endpoint? */
		if ((iface->ep_desc[i].bmAttributes &
		     USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
			u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
			if (ep_addr & USB_DIR_IN) {
				if (!ep_in_found) {
					ss->ep_in = ep_addr &
						USB_ENDPOINT_NUMBER_MASK;
					ep_in_found = 1;
				}
			} else {
				if (!ep_out_found) {
					ss->ep_out = ep_addr &
						USB_ENDPOINT_NUMBER_MASK;
					ep_out_found = 1;
				}
			}
		}

		/* is it an interrupt endpoint? */
		if ((iface->ep_desc[i].bmAttributes &
		    USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
			ss->ep_int = iface->ep_desc[i].bEndpointAddress &
				USB_ENDPOINT_NUMBER_MASK;
			ss->irqinterval = iface->ep_desc[i].bInterval;
		}
	}
	debug("Endpoints In %d Out %d Int %d\n",
		  ss->ep_in, ss->ep_out, ss->ep_int);

	/* Do some basic sanity checks, and bail if we find a problem */
	if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
	    !ss->ep_in || !ss->ep_out || !ss->ep_int) {
		debug("Problems with device\n");
		return 0;
	}
	dev->privptr = (void *)ss;
	return 1;
}

int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
				struct eth_device *eth)
{
	struct asix_private *priv = (struct asix_private *)ss->dev_priv;

	if (!eth) {
		debug("%s: missing parameter.\n", __func__);
		return 0;
	}
	sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
	eth->init = asix_init;
	eth->send = asix_send;
	eth->recv = asix_recv;
	eth->halt = asix_halt;
	if (!(priv->flags & FLAG_TYPE_AX88172))
		eth->write_hwaddr = asix_write_hwaddr;
	eth->priv = ss;

	if (asix_basic_reset(ss))
		return 0;

	/* Get the MAC address */
	if (asix_read_mac(eth))
		return 0;
	debug("MAC %pM\n", eth->enetaddr);

	return 1;
}
Commit	Line	Data
9b70e007 SG	1	/*
	2	* Copyright (c) 2011 The Chromium OS Authors.
	3	* See file CREDITS for list of people who contributed to this
	4	* project.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <common.h>
	23	#include <usb.h>
	24	#include <linux/mii.h>
	25	#include "usb_ether.h"
58f8fab8	26	#include <malloc.h>
9b70e007 SG	27
	28
	29	/* ASIX AX8817X based USB 2.0 Ethernet Devices */
	30
	31	#define AX_CMD_SET_SW_MII 0x06
	32	#define AX_CMD_READ_MII_REG 0x07
	33	#define AX_CMD_WRITE_MII_REG 0x08
	34	#define AX_CMD_SET_HW_MII 0x0a
02c8d8cc	35	#define AX_CMD_READ_EEPROM 0x0b
9b70e007 SG	36	#define AX_CMD_READ_RX_CTL 0x0f
	37	#define AX_CMD_WRITE_RX_CTL 0x10
	38	#define AX_CMD_WRITE_IPG0 0x12
	39	#define AX_CMD_READ_NODE_ID 0x13
58f8fab8	40	#define AX_CMD_WRITE_NODE_ID 0x14
9b70e007 SG	41	#define AX_CMD_READ_PHY_ID 0x19
	42	#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
	43	#define AX_CMD_WRITE_GPIOS 0x1f
	44	#define AX_CMD_SW_RESET 0x20
	45	#define AX_CMD_SW_PHY_SELECT 0x22
	46
	47	#define AX_SWRESET_CLEAR 0x00
	48	#define AX_SWRESET_PRTE 0x04
	49	#define AX_SWRESET_PRL 0x08
	50	#define AX_SWRESET_IPRL 0x20
	51	#define AX_SWRESET_IPPD 0x40
	52
	53	#define AX88772_IPG0_DEFAULT 0x15
	54	#define AX88772_IPG1_DEFAULT 0x0c
	55	#define AX88772_IPG2_DEFAULT 0x12
	56
	57	/* AX88772 & AX88178 Medium Mode Register */
	58	#define AX_MEDIUM_PF 0x0080
	59	#define AX_MEDIUM_JFE 0x0040
	60	#define AX_MEDIUM_TFC 0x0020
	61	#define AX_MEDIUM_RFC 0x0010
	62	#define AX_MEDIUM_ENCK 0x0008
	63	#define AX_MEDIUM_AC 0x0004
	64	#define AX_MEDIUM_FD 0x0002
	65	#define AX_MEDIUM_GM 0x0001
	66	#define AX_MEDIUM_SM 0x1000
	67	#define AX_MEDIUM_SBP 0x0800
	68	#define AX_MEDIUM_PS 0x0200
	69	#define AX_MEDIUM_RE 0x0100
	70
	71	#define AX88178_MEDIUM_DEFAULT \
	72	(AX_MEDIUM_PS \| AX_MEDIUM_FD \| AX_MEDIUM_AC \| \
	73	AX_MEDIUM_RFC \| AX_MEDIUM_TFC \| AX_MEDIUM_JFE \| \
	74	AX_MEDIUM_RE)
	75
	76	#define AX88772_MEDIUM_DEFAULT \
	77	(AX_MEDIUM_FD \| AX_MEDIUM_RFC \| \
	78	AX_MEDIUM_TFC \| AX_MEDIUM_PS \| \
	79	AX_MEDIUM_AC \| AX_MEDIUM_RE)
	80
	81	/* AX88772 & AX88178 RX_CTL values */
	82	#define AX_RX_CTL_SO 0x0080
	83	#define AX_RX_CTL_AB 0x0008
	84
	85	#define AX_DEFAULT_RX_CTL \
	86	(AX_RX_CTL_SO \| AX_RX_CTL_AB)
	87
	88	/* GPIO 2 toggles */
	89	#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
	90	#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
	91	#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
	92
	93	/* local defines */
	94	#define ASIX_BASE_NAME "asx"
	95	#define USB_CTRL_SET_TIMEOUT 5000
	96	#define USB_CTRL_GET_TIMEOUT 5000
	97	#define USB_BULK_SEND_TIMEOUT 5000
	98	#define USB_BULK_RECV_TIMEOUT 5000
	99
	100	#define AX_RX_URB_SIZE 2048
	101	#define PHY_CONNECT_TIMEOUT 5000
	102
58f8fab8 LS	103	/* asix_flags defines */
	104	#define FLAG_NONE 0
	105	#define FLAG_TYPE_AX88172 (1U << 0)
	106	#define FLAG_TYPE_AX88772 (1U << 1)
1dff9d0f LS	107	#define FLAG_TYPE_AX88772B (1U << 2)
1dff9d0f LS	108	#define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
58f8fab8	109
9b70e007 SG	110	/* local vars */
	111	static int curr_eth_dev; /* index for name of next device detected */
	112
58f8fab8 LS	113	/* driver private */
	114	struct asix_private {
	115	int flags;
	116	};
	117
9b70e007 SG	118	/*
	119	* Asix infrastructure commands
	120	*/
	121	static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
	122	u16 size, void *data)
	123	{
	124	int len;
	125
	126	debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
	127	"size=%d\n", cmd, value, index, size);
	128
	129	len = usb_control_msg(
	130	dev->pusb_dev,
	131	usb_sndctrlpipe(dev->pusb_dev, 0),
	132	cmd,
	133	USB_DIR_OUT \| USB_TYPE_VENDOR \| USB_RECIP_DEVICE,
	134	value,
	135	index,
	136	data,
	137	size,
	138	USB_CTRL_SET_TIMEOUT);
	139
	140	return len == size ? 0 : -1;
	141	}
	142
	143	static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
	144	u16 size, void *data)
	145	{
	146	int len;
	147
	148	debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
	149	cmd, value, index, size);
	150
	151	len = usb_control_msg(
	152	dev->pusb_dev,
	153	usb_rcvctrlpipe(dev->pusb_dev, 0),
	154	cmd,
	155	USB_DIR_IN \| USB_TYPE_VENDOR \| USB_RECIP_DEVICE,
	156	value,
	157	index,
	158	data,
	159	size,
	160	USB_CTRL_GET_TIMEOUT);
	161	return len == size ? 0 : -1;
	162	}
	163
	164	static inline int asix_set_sw_mii(struct ueth_data *dev)
	165	{
	166	int ret;
	167
	168	ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
	169	if (ret < 0)
	170	debug("Failed to enable software MII access\n");
	171	return ret;
	172	}
	173
	174	static inline int asix_set_hw_mii(struct ueth_data *dev)
	175	{
	176	int ret;
	177
	178	ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
	179	if (ret < 0)
	180	debug("Failed to enable hardware MII access\n");
	181	return ret;
182	}
183
184	static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
185	{
c59ab092	186	ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
9b70e007 SG	187
9b70e007 SG	188	asix_set_sw_mii(dev);
c59ab092	189	asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
9b70e007 SG	190	asix_set_hw_mii(dev);
	191
	192	debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
c59ab092	193	phy_id, loc, le16_to_cpu(*res));
9b70e007	194
c59ab092	195	return le16_to_cpu(*res);
9b70e007 SG	196	}
	197
	198	static void
	199	asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
	200	{
c59ab092 MV	201	ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
c59ab092 MV	202	*res = cpu_to_le16(val);
9b70e007 SG	203
	204	debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
	205	phy_id, loc, val);
	206	asix_set_sw_mii(dev);
c59ab092	207	asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
9b70e007 SG	208	asix_set_hw_mii(dev);
	209	}
	210
	211	/*
	212	* Asix "high level" commands
	213	*/
	214	static int asix_sw_reset(struct ueth_data *dev, u8 flags)
	215	{
	216	int ret;
	217
	218	ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
	219	if (ret < 0)
	220	debug("Failed to send software reset: %02x\n", ret);
	221	else
	222	udelay(150 * 1000);
	223
	224	return ret;
	225	}
	226
	227	static inline int asix_get_phy_addr(struct ueth_data *dev)
	228	{
c59ab092 MV	229	ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
c59ab092 MV	230
9b70e007 SG	231	int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
	232
	233	debug("asix_get_phy_addr()\n");
	234
	235	if (ret < 0) {
	236	debug("Error reading PHYID register: %02x\n", ret);
	237	goto out;
	238	}
0ed1eb6f	239	debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
9b70e007 SG	240	ret = buf[1];
	241
	242	out:
	243	return ret;
	244	}
	245
	246	static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
	247	{
	248	int ret;
	249
	250	debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
	251	ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
	252	0, 0, NULL);
	253	if (ret < 0) {
	254	debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
	255	mode, ret);
	256	}
	257	return ret;
	258	}
	259
	260	static u16 asix_read_rx_ctl(struct ueth_data *dev)
	261	{
c59ab092 MV	262	ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
	263
	264	int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
9b70e007 SG	265
	266	if (ret < 0)
	267	debug("Error reading RX_CTL register: %02x\n", ret);
	268	else
c59ab092	269	ret = le16_to_cpu(*v);
9b70e007 SG	270	return ret;
	271	}
	272
	273	static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
	274	{
	275	int ret;
	276
	277	debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
	278	ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
	279	if (ret < 0) {
	280	debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
	281	mode, ret);
	282	}
	283	return ret;
	284	}
	285
	286	static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
	287	{
	288	int ret;
	289
	290	debug("asix_write_gpio() - value = 0x%04x\n", value);
	291	ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
	292	if (ret < 0) {
	293	debug("Failed to write GPIO value 0x%04x: %02x\n",
	294	value, ret);
	295	}
	296	if (sleep)
	297	udelay(sleep * 1000);
	298
	299	return ret;
	300	}
	301
58f8fab8 LS	302	static int asix_write_hwaddr(struct eth_device *eth)
	303	{
	304	struct ueth_data dev = (struct ueth_data )eth->priv;
	305	int ret;
	306	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
	307
	308	memcpy(buf, eth->enetaddr, ETH_ALEN);
	309
	310	ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
	311	if (ret < 0)
	312	debug("Failed to set MAC address: %02x\n", ret);
	313
	314	return ret;
	315	}
	316
9b70e007 SG	317	/*
	318	* mii commands
	319	*/
	320
	321	/*
	322	* mii_nway_restart - restart NWay (autonegotiation) for this interface
	323	*
	324	* Returns 0 on success, negative on error.
	325	*/
	326	static int mii_nway_restart(struct ueth_data *dev)
	327	{
	328	int bmcr;
	329	int r = -1;
	330
	331	/* if autoneg is off, it's an error */
	332	bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
	333
	334	if (bmcr & BMCR_ANENABLE) {
	335	bmcr \|= BMCR_ANRESTART;
	336	asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
	337	r = 0;
	338	}
	339
	340	return r;
	341	}
	342
02c8d8cc LS	343	static int asix_read_mac(struct eth_device *eth)
	344	{
	345	struct ueth_data dev = (struct ueth_data )eth->priv;
	346	struct asix_private priv = (struct asix_private )dev->dev_priv;
	347	int i;
	348	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
	349
	350	if (priv->flags & FLAG_EEPROM_MAC) {
	351	for (i = 0; i < (ETH_ALEN >> 1); i++) {
	352	if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
	353	0x04 + i, 0, 2, buf) < 0) {
	354	debug("Failed to read SROM address 04h.\n");
	355	return -1;
	356	}
	357	memcpy((eth->enetaddr + i * 2), buf, 2);
	358	}
	359	} else {
	360	if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
	361	< 0) {
	362	debug("Failed to read MAC address.\n");
	363	return -1;
	364	}
	365	memcpy(eth->enetaddr, buf, ETH_ALEN);
	366	}
	367
	368	return 0;
	369	}
	370
5fae53d0	371	static int asix_basic_reset(struct ueth_data *dev)
9b70e007 SG	372	{
9b70e007 SG	373	int embd_phy;
9b70e007	374	u16 rx_ctl;
9b70e007 SG	375
	376	if (asix_write_gpio(dev,
	377	AX_GPIO_RSE \| AX_GPIO_GPO_2 \| AX_GPIO_GPO2EN, 5) < 0)
5fae53d0	378	return -1;
9b70e007 SG	379
	380	/* 0x10 is the phy id of the embedded 10/100 ethernet phy */
	381	embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
	382	if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
	383	embd_phy, 0, 0, NULL) < 0) {
	384	debug("Select PHY #1 failed\n");
5fae53d0	385	return -1;
9b70e007 SG	386	}
	387
	388	if (asix_sw_reset(dev, AX_SWRESET_IPPD \| AX_SWRESET_PRL) < 0)
5fae53d0	389	return -1;
9b70e007 SG	390
9b70e007 SG	391	if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
5fae53d0	392	return -1;
9b70e007 SG	393
	394	if (embd_phy) {
	395	if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
5fae53d0	396	return -1;
9b70e007 SG	397	} else {
9b70e007 SG	398	if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
5fae53d0	399	return -1;
9b70e007 SG	400	}
	401
	402	rx_ctl = asix_read_rx_ctl(dev);
	403	debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
	404	if (asix_write_rx_ctl(dev, 0x0000) < 0)
5fae53d0	405	return -1;
9b70e007 SG	406
	407	rx_ctl = asix_read_rx_ctl(dev);
	408	debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
	409
5fae53d0 LS	410	return 0;
	411	}
	412
	413	/*
	414	* Asix callbacks
	415	*/
	416	static int asix_init(struct eth_device eth, bd_t bd)
	417	{
	418	struct ueth_data dev = (struct ueth_data )eth->priv;
	419	int timeout = 0;
	420	#define TIMEOUT_RESOLUTION 50 /* ms */
	421	int link_detected;
	422
	423	debug("** %s()\n", __func__);
	424
9b70e007 SG	425	dev->phy_id = asix_get_phy_addr(dev);
	426	if (dev->phy_id < 0)
	427	debug("Failed to read phy id\n");
	428
	429	if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0)
	430	goto out_err;
	431
	432	if (asix_sw_reset(dev, AX_SWRESET_IPRL \| AX_SWRESET_PRL) < 0)
	433	goto out_err;
	434
	435	asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
	436	asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
	437	ADVERTISE_ALL \| ADVERTISE_CSMA);
	438	mii_nway_restart(dev);
	439
	440	if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
	441	goto out_err;
	442
	443	if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
	444	AX88772_IPG0_DEFAULT \| AX88772_IPG1_DEFAULT,
	445	AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
	446	debug("Write IPG,IPG1,IPG2 failed\n");
	447	goto out_err;
	448	}
	449
	450	if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
	451	goto out_err;
	452
	453	do {
	454	link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
	455	BMSR_LSTATUS;
	456	if (!link_detected) {
	457	if (timeout == 0)
	458	printf("Waiting for Ethernet connection... ");
	459	udelay(TIMEOUT_RESOLUTION * 1000);
	460	timeout += TIMEOUT_RESOLUTION;
	461	}
	462	} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
	463	if (link_detected) {
	464	if (timeout != 0)
	465	printf("done.\n");
	466	} else {
	467	printf("unable to connect.\n");
	468	goto out_err;
	469	}
	470
	471	return 0;
	472	out_err:
	473	return -1;
	474	}
	475
e14826bc	476	static int asix_send(struct eth_device eth, void packet, int length)
9b70e007 SG	477	{
	478	struct ueth_data dev = (struct ueth_data )eth->priv;
	479	int err;
	480	u32 packet_len;
	481	int actual_len;
c59ab092 MV	482	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
c59ab092 MV	483	PKTSIZE + sizeof(packet_len));
9b70e007 SG	484
	485	debug("** %s(), len %d\n", __func__, length);
	486
	487	packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
	488	cpu_to_le32s(&packet_len);
	489
	490	memcpy(msg, &packet_len, sizeof(packet_len));
	491	memcpy(msg + sizeof(packet_len), (void *)packet, length);
	492	if (length & 1)
	493	length++;
	494
	495	err = usb_bulk_msg(dev->pusb_dev,
	496	usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
	497	(void *)msg,
	498	length + sizeof(packet_len),
	499	&actual_len,
	500	USB_BULK_SEND_TIMEOUT);
	501	debug("Tx: len = %u, actual = %u, err = %d\n",
	502	length + sizeof(packet_len), actual_len, err);
	503
	504	return err;
	505	}
	506
	507	static int asix_recv(struct eth_device *eth)
	508	{
	509	struct ueth_data dev = (struct ueth_data )eth->priv;
c59ab092	510	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
9b70e007 SG	511	unsigned char *buf_ptr;
	512	int err;
	513	int actual_len;
	514	u32 packet_len;
	515
	516	debug("** %s()\n", __func__);
	517
	518	err = usb_bulk_msg(dev->pusb_dev,
	519	usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
	520	(void *)recv_buf,
	521	AX_RX_URB_SIZE,
	522	&actual_len,
	523	USB_BULK_RECV_TIMEOUT);
	524	debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
	525	actual_len, err);
	526	if (err != 0) {
	527	debug("Rx: failed to receive\n");
	528	return -1;
	529	}
	530	if (actual_len > AX_RX_URB_SIZE) {
	531	debug("Rx: received too many bytes %d\n", actual_len);
	532	return -1;
	533	}
	534
	535	buf_ptr = recv_buf;
	536	while (actual_len > 0) {
	537	/*
	538	* 1st 4 bytes contain the length of the actual data as two
	539	* complementary 16-bit words. Extract the length of the data.
	540	*/
	541	if (actual_len < sizeof(packet_len)) {
	542	debug("Rx: incomplete packet length\n");
	543	return -1;
	544	}
	545	memcpy(&packet_len, buf_ptr, sizeof(packet_len));
	546	le32_to_cpus(&packet_len);
1dff9d0f	547	if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
9b70e007	548	debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
1dff9d0f LS	549	packet_len, (~packet_len >> 16) & 0x7ff,
1dff9d0f LS	550	packet_len & 0x7ff);
9b70e007 SG	551	return -1;
9b70e007 SG	552	}
1dff9d0f	553	packet_len = packet_len & 0x7ff;
9b70e007 SG	554	if (packet_len > actual_len - sizeof(packet_len)) {
	555	debug("Rx: too large packet: %d\n", packet_len);
	556	return -1;
	557	}
	558
	559	/* Notify net stack */
	560	NetReceive(buf_ptr + sizeof(packet_len), packet_len);
	561
	562	/* Adjust for next iteration. Packets are padded to 16-bits */
	563	if (packet_len & 1)
	564	packet_len++;
	565	actual_len -= sizeof(packet_len) + packet_len;
	566	buf_ptr += sizeof(packet_len) + packet_len;
	567	}
	568
	569	return err;
	570	}
	571
	572	static void asix_halt(struct eth_device *eth)
	573	{
	574	debug("** %s()\n", __func__);
	575	}
	576
	577	/*
	578	* Asix probing functions
	579	*/
	580	void asix_eth_before_probe(void)
	581	{
	582	curr_eth_dev = 0;
	583	}
	584
	585	struct asix_dongle {
	586	unsigned short vendor;
	587	unsigned short product;
58f8fab8	588	int flags;
9b70e007 SG	589	};
9b70e007 SG	590
58f8fab8 LS	591	static const struct asix_dongle const asix_dongles[] = {
	592	{ 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
	593	{ 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
	594	/* Cables-to-Go USB Ethernet Adapter */
	595	{ 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
	596	{ 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
	597	{ 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
	598	{ 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
	599	{ 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
	600	{ 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
	601	/* DLink DUB-E100 H/W Ver B1 Alternate */
	602	{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
1dff9d0f LS	603	/* ASIX 88772B */
1dff9d0f LS	604	{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B \| FLAG_EEPROM_MAC },
58f8fab8	605	{ 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
9b70e007 SG	606	};
	607
	608	/* Probe to see if a new device is actually an asix device */
	609	int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
	610	struct ueth_data *ss)
	611	{
	612	struct usb_interface *iface;
	613	struct usb_interface_descriptor *iface_desc;
1dff9d0f	614	int ep_in_found = 0, ep_out_found = 0;
9b70e007 SG	615	int i;
	616
	617	/* let's examine the device now */
	618	iface = &dev->config.if_desc[ifnum];
	619	iface_desc = &dev->config.if_desc[ifnum].desc;
	620
	621	for (i = 0; asix_dongles[i].vendor != 0; i++) {
	622	if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
	623	dev->descriptor.idProduct == asix_dongles[i].product)
	624	/* Found a supported dongle */
	625	break;
	626	}
	627
	628	if (asix_dongles[i].vendor == 0)
	629	return 0;
	630
	631	memset(ss, 0, sizeof(struct ueth_data));
	632
	633	/* At this point, we know we've got a live one */
	634	debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
	635	dev->descriptor.idVendor, dev->descriptor.idProduct);
	636
	637	/* Initialize the ueth_data structure with some useful info */
	638	ss->ifnum = ifnum;
	639	ss->pusb_dev = dev;
	640	ss->subclass = iface_desc->bInterfaceSubClass;
	641	ss->protocol = iface_desc->bInterfaceProtocol;
	642
58f8fab8 LS	643	/* alloc driver private */
	644	ss->dev_priv = calloc(1, sizeof(struct asix_private));
	645	if (!ss->dev_priv)
	646	return 0;
	647
	648	((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
	649
9b70e007 SG	650	/*
	651	* We are expecting a minimum of 3 endpoints - in, out (bulk), and
	652	* int. We will ignore any others.
	653	*/
	654	for (i = 0; i < iface_desc->bNumEndpoints; i++) {
	655	/* is it an BULK endpoint? */
	656	if ((iface->ep_desc[i].bmAttributes &
	657	USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1dff9d0f LS	658	u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
	659	if (ep_addr & USB_DIR_IN) {
	660	if (!ep_in_found) {
	661	ss->ep_in = ep_addr &
	662	USB_ENDPOINT_NUMBER_MASK;
	663	ep_in_found = 1;
	664	}
	665	} else {
	666	if (!ep_out_found) {
	667	ss->ep_out = ep_addr &
	668	USB_ENDPOINT_NUMBER_MASK;
	669	ep_out_found = 1;
	670	}
	671	}
9b70e007 SG	672	}
	673
	674	/* is it an interrupt endpoint? */
	675	if ((iface->ep_desc[i].bmAttributes &
	676	USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
	677	ss->ep_int = iface->ep_desc[i].bEndpointAddress &
	678	USB_ENDPOINT_NUMBER_MASK;
	679	ss->irqinterval = iface->ep_desc[i].bInterval;
	680	}
	681	}
	682	debug("Endpoints In %d Out %d Int %d\n",
	683	ss->ep_in, ss->ep_out, ss->ep_int);
	684
	685	/* Do some basic sanity checks, and bail if we find a problem */
	686	if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) \|\|
	687	!ss->ep_in \|\| !ss->ep_out \|\| !ss->ep_int) {
	688	debug("Problems with device\n");
	689	return 0;
	690	}
	691	dev->privptr = (void *)ss;
	692	return 1;
	693	}
	694
	695	int asix_eth_get_info(struct usb_device dev, struct ueth_data ss,
	696	struct eth_device *eth)
	697	{
58f8fab8 LS	698	struct asix_private priv = (struct asix_private )ss->dev_priv;
58f8fab8 LS	699
9b70e007 SG	700	if (!eth) {
	701	debug("%s: missing parameter.\n", __func__);
	702	return 0;
	703	}
	704	sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
	705	eth->init = asix_init;
	706	eth->send = asix_send;
	707	eth->recv = asix_recv;
	708	eth->halt = asix_halt;
58f8fab8 LS	709	if (!(priv->flags & FLAG_TYPE_AX88172))
58f8fab8 LS	710	eth->write_hwaddr = asix_write_hwaddr;
9b70e007 SG	711	eth->priv = ss;
9b70e007 SG	712
5fae53d0 LS	713	if (asix_basic_reset(ss))
	714	return 0;
	715
02c8d8cc LS	716	/* Get the MAC address */
	717	if (asix_read_mac(eth))
	718	return 0;
	719	debug("MAC %pM\n", eth->enetaddr);
	720
9b70e007 SG	721	return 1;
9b70e007 SG	722	}