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439321b2 PF |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Copyright 2019 NXP | |
4 | */ | |
5 | ||
6 | #ifndef __IMX8MP_EVK_H | |
7 | #define __IMX8MP_EVK_H | |
8 | ||
9 | #include <linux/sizes.h> | |
1af3c7f4 | 10 | #include <linux/stringify.h> |
439321b2 PF |
11 | #include <asm/arch/imx-regs.h> |
12 | ||
439321b2 PF |
13 | #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
14 | ||
15 | #ifdef CONFIG_SPL_BUILD | |
16 | /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ | |
439321b2 | 17 | |
439321b2 | 18 | |
439321b2 PF |
19 | #define CONFIG_POWER_PCA9450 |
20 | ||
439321b2 PF |
21 | #endif |
22 | ||
48b90f86 | 23 | #if defined(CONFIG_CMD_NET) |
48b90f86 | 24 | #define CONFIG_FEC_MXC_PHYADDR 1 |
48b90f86 | 25 | |
48b90f86 PF |
26 | #define PHY_ANEG_TIMEOUT 20000 |
27 | ||
28 | #endif | |
29 | ||
9b162b1d AG |
30 | #define BOOT_TARGET_DEVICES(func) \ |
31 | func(MMC, mmc, 1) \ | |
32 | func(MMC, mmc, 2) | |
33 | ||
34 | #include <config_distro_bootcmd.h> | |
9b162b1d | 35 | |
439321b2 PF |
36 | /* Initial environment variables */ |
37 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
9b162b1d | 38 | BOOTENV \ |
72d81360 TR |
39 | "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
40 | "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
439321b2 PF |
41 | "image=Image\0" \ |
42 | "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ | |
a0273593 | 43 | "fdt_addr_r=0x43000000\0" \ |
439321b2 | 44 | "boot_fdt=try\0" \ |
a0273593 | 45 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
439321b2 | 46 | "initrd_addr=0x43800000\0" \ |
acbc1d86 | 47 | "bootm_size=0x10000000\0" \ |
de35b8f9 | 48 | "mmcpart=1\0" \ |
adfaa428 | 49 | "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ |
439321b2 PF |
50 | |
51 | /* Link Definitions */ | |
439321b2 PF |
52 | |
53 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 | |
54 | #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 | |
439321b2 | 55 | |
439321b2 | 56 | |
864ac2cf | 57 | /* Totally 2GB DDR */ |
439321b2 PF |
58 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
59 | #define PHYS_SDRAM 0x40000000 | |
864ac2cf | 60 | #define PHYS_SDRAM_SIZE 0x80000000 |
439321b2 | 61 | |
439321b2 | 62 | #endif |