[u-boot.git] / include / configs / M5208EVBE.h

/*
 * Configuation settings for the Freescale MCF5208EVBe.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _M5208EVBE_H
#define _M5208EVBE_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT		5000

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5208EVBe
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 3ffff;"		\
	"era 0 3ffff;"				\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
#define CONFIG_SYS_LOAD_ADDR	0x40010000

#define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
#define CONFIG_SYS_PLL_ODR	0x36
#define CONFIG_SYS_PLL_FDR	0x7D

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
#define CONFIG_SYS_SDRAM_EMOD		0x80010000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER		1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	254	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/*
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		0x2000
#define CONFIG_ENV_SIZE			0x1000
#define CONFIG_ENV_SECT_SIZE		0x2000

#define LDS_BOARD_TEXT \
        . = DEFINED(env_offset) ? env_offset : .; \
        common/env_embedded.o (.text*);

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/* Chipselect bank definitions */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x007F0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0

#endif				/* _M5208EVBE_H */
Commit	Line	Data
bf9a5215 TL	1	/*
	2	* Configuation settings for the Freescale MCF5208EVBe.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew ([email protected])
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
bf9a5215 TL	8	*/
	9
	10	#ifndef _M5208EVBE_H
	11	#define _M5208EVBE_H
	12
	13	/*
	14	* High Level Configuration Options
	15	* (easy to change)
	16	*/
bf9a5215 TL	17	#define CONFIG_MCFUART
bf9a5215 TL	18	#define CONFIG_SYS_UART_PORT (0)
bf9a5215 TL	19
	20	#undef CONFIG_WATCHDOG
	21	#define CONFIG_WATCHDOG_TIMEOUT 5000
	22
bf9a5215 TL	23	#define CONFIG_MCFFEC
bf9a5215 TL	24	#ifdef CONFIG_MCFFEC
bf9a5215 TL	25	# define CONFIG_MII 1
	26	# define CONFIG_MII_INIT 1
	27	# define CONFIG_SYS_DISCOVER_PHY
	28	# define CONFIG_SYS_RX_ETH_BUFFER 8
	29	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	30	# define CONFIG_HAS_ETH1
	31
	32	# define CONFIG_SYS_FEC0_PINMUX 0
	33	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	34	# define MCFFEC_TOUT_LOOP 50000
	35	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
	36	# ifndef CONFIG_SYS_DISCOVER_PHY
	37	# define FECDUPLEX FULL
	38	# define FECSPEED _100BASET
	39	# else
	40	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	41	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	42	# endif
	43	# endif /* CONFIG_SYS_DISCOVER_PHY */
	44	#endif
	45
	46	/* Timer */
	47	#define CONFIG_MCFTMR
	48	#undef CONFIG_MCFPIT
	49
	50	/* I2C */
00f792e0 HS	51	#define CONFIG_SYS_I2C
	52	#define CONFIG_SYS_I2C_FSL
	53	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	54	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	55	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
bf9a5215 TL	56	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
bf9a5215 TL	57
bf9a5215 TL	58	#define CONFIG_UDP_CHECKSUM
	59
	60	#ifdef CONFIG_MCFFEC
bf9a5215 TL	61	# define CONFIG_IPADDR 192.162.1.2
	62	# define CONFIG_NETMASK 255.255.255.0
	63	# define CONFIG_SERVERIP 192.162.1.1
	64	# define CONFIG_GATEWAYIP 192.162.1.1
bf9a5215 TL	65	#endif /* CONFIG_MCFFEC */
	66
	67	#define CONFIG_HOSTNAME M5208EVBe
	68	#define CONFIG_EXTRA_ENV_SETTINGS \
	69	"netdev=eth0\0" \
	70	"loadaddr=40010000\0" \
	71	"u-boot=u-boot.bin\0" \
	72	"load=tftp ${loadaddr) ${u-boot}\0" \
	73	"upd=run load; run prog\0" \
	74	"prog=prot off 0 3ffff;" \
	75	"era 0 3ffff;" \
	76	"cp.b ${loadaddr} 0 ${filesize};" \
	77	"save\0" \
	78	""
	79
	80	#define CONFIG_PRAM 512 /* 512 KB */
bf9a5215 TL	81	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	82
	83	#ifdef CONFIG_CMD_KGDB
	84	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	85	#else
	86	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	87	#endif
	88
	89	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	90	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
	91	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
	92	#define CONFIG_SYS_LOAD_ADDR 0x40010000
	93
bf9a5215 TL	94	#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
	95	#define CONFIG_SYS_PLL_ODR 0x36
	96	#define CONFIG_SYS_PLL_FDR 0x7D
	97
	98	#define CONFIG_SYS_MBAR 0xFC000000
	99
	100	/*
	101	* Low Level Configuration Settings
	102	* (address mappings, register initial values, etc.)
	103	* You should know what you are doing if you make changes here.
	104	*/
	105	/* Definitions for initial stack pointer and data area (in DPRAM) */
	106	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	107	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
bf9a5215	108	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	109	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
bf9a5215 TL	110	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	111
	112	/*
	113	* Start addresses for the final memory configuration
	114	* (Set up by the startup code)
	115	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	116	*/
	117	#define CONFIG_SYS_SDRAM_BASE 0x40000000
f628e2f7	118	#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
bf9a5215 TL	119	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	120	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	121	#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
	122	#define CONFIG_SYS_SDRAM_EMOD 0x80010000
	123	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
	124
	125	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	126	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	127
	128	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	129	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	130
	131	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	132	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	133
	134	/*
	135	* For booting Linux, the board info and command line data
	136	* have to be in the first 8 MB of memory, since this is
	137	* the maximum mapped by the Linux kernel during initialization ??
	138	*/
	139	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
	140	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
	141
	142	/* FLASH organization */
	143	#define CONFIG_SYS_FLASH_CFI
	144	#ifdef CONFIG_SYS_FLASH_CFI
	145	# define CONFIG_FLASH_CFI_DRIVER 1
	146	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	147	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	148	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	149	# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
	150	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	151	#endif
	152
	153	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	154
	155	/*
	156	* Configuration for environment
	157	* Environment is embedded in u-boot in the second sector of the flash
	158	*/
	159	#define CONFIG_ENV_OFFSET 0x2000
	160	#define CONFIG_ENV_SIZE 0x1000
	161	#define CONFIG_ENV_SECT_SIZE 0x2000
bf9a5215	162
5296cb1d	163	#define LDS_BOARD_TEXT \
	164	. = DEFINED(env_offset) ? env_offset : .; \
	165	common/env_embedded.o (.text*);
	166
bf9a5215 TL	167	/* Cache Configuration */
	168	#define CONFIG_SYS_CACHELINE_SIZE 16
	169
dd9f054e	170	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	171	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	172	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	173	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	174	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	175	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	176	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	177	CF_ACR_EN \| CF_ACR_SM_ALL)
	178	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	179	CF_CACR_DISD \| CF_CACR_INVI \| \
	180	CF_CACR_CEIB \| CF_CACR_DCM \| \
	181	CF_CACR_EUSP)
	182
bf9a5215 TL	183	/* Chipselect bank definitions */
	184	/*
	185	* CS0 - NOR Flash
	186	* CS1 - Available
	187	* CS2 - Available
	188	* CS3 - Available
	189	* CS4 - Available
	190	* CS5 - Available
	191	*/
	192	#define CONFIG_SYS_CS0_BASE 0
	193	#define CONFIG_SYS_CS0_MASK 0x007F0001
	194	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	195
	196	#endif /* _M5208EVBE_H */