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ece92f85 JJ |
1 | /**************************************************************************** |
2 | * | |
9c7e4b06 | 3 | * Video BOOT Graphics Card POST Module |
ece92f85 JJ |
4 | * |
5 | * ======================================================================== | |
4c2e3da8 | 6 | * Copyright (C) 2007 Freescale Semiconductor, Inc. |
ece92f85 JJ |
7 | * Jason Jin <[email protected]> |
8 | * | |
9 | * Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved. | |
10 | * | |
11 | * This file may be distributed and/or modified under the terms of the | |
12 | * GNU General Public License version 2.0 as published by the Free | |
13 | * Software Foundation and appearing in the file LICENSE.GPL included | |
14 | * in the packaging of this file. | |
15 | * | |
16 | * Licensees holding a valid Commercial License for this product from | |
17 | * SciTech Software, Inc. may use this file in accordance with the | |
18 | * Commercial License Agreement provided with the Software. | |
19 | * | |
20 | * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING | |
21 | * THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
22 | * PURPOSE. | |
23 | * | |
24 | * See http://www.scitechsoft.com/license/ for information about | |
25 | * the licensing options available and how to purchase a Commercial | |
26 | * License Agreement. | |
27 | * | |
28 | * Contact [email protected] if any conditions of this licensing | |
29 | * are not clear to you, or you have questions about licensing options. | |
30 | * | |
31 | * ======================================================================== | |
32 | * | |
9c7e4b06 WD |
33 | * Language: ANSI C |
34 | * Environment: Linux Kernel | |
35 | * Developer: Kendall Bennett | |
ece92f85 | 36 | * |
9c7e4b06 WD |
37 | * Description: Module to implement booting PCI/AGP controllers on the |
38 | * bus. We use the x86 real mode emulator to run the BIOS on | |
39 | * graphics controllers to bring the cards up. | |
ece92f85 | 40 | * |
9c7e4b06 WD |
41 | * Note that at present this module does *not* support |
42 | * multiple controllers. | |
ece92f85 | 43 | * |
9c7e4b06 WD |
44 | * The orignal name of this file is warmboot.c. |
45 | * Jason ported this file to u-boot to run the ATI video card | |
46 | * BIOS in u-boot. | |
ece92f85 JJ |
47 | ****************************************************************************/ |
48 | #include <common.h> | |
4c59f953 SG |
49 | #include <bios_emul.h> |
50 | #include <errno.h> | |
ece92f85 | 51 | #include <malloc.h> |
4c59f953 SG |
52 | #include <vbe.h> |
53 | #include "biosemui.h" | |
ece92f85 JJ |
54 | |
55 | /* Length of the BIOS image */ | |
9c7e4b06 | 56 | #define MAX_BIOSLEN (128 * 1024L) |
ece92f85 | 57 | |
ece92f85 JJ |
58 | /* Place to save PCI BAR's that we change and later restore */ |
59 | static u32 saveROMBaseAddress; | |
60 | static u32 saveBaseAddress10; | |
61 | static u32 saveBaseAddress14; | |
62 | static u32 saveBaseAddress18; | |
63 | static u32 saveBaseAddress20; | |
64 | ||
4c59f953 SG |
65 | static void atibios_set_vesa_mode(RMREGS *regs, int vesa_mode, |
66 | struct vbe_mode_info *mode_info) | |
67 | { | |
68 | debug("VBE: Setting VESA mode %#04x\n", vesa_mode); | |
69 | /* request linear framebuffer mode */ | |
70 | vesa_mode |= (1 << 14); | |
71 | /* request clearing of framebuffer */ | |
72 | vesa_mode &= ~(1 << 15); | |
73 | regs->e.eax = VESA_SET_MODE; | |
74 | regs->e.ebx = vesa_mode; | |
75 | BE_int86(0x10, regs, regs); | |
76 | ||
77 | int offset = 0x2000; | |
78 | void *buffer = (void *)(M.mem_base + offset); | |
79 | ||
80 | u16 buffer_seg = (((unsigned long)offset) >> 4) & 0xff00; | |
81 | u16 buffer_adr = ((unsigned long)offset) & 0xffff; | |
82 | regs->e.eax = VESA_GET_MODE_INFO; | |
83 | regs->e.ebx = 0; | |
84 | regs->e.ecx = vesa_mode; | |
85 | regs->e.edx = 0; | |
86 | regs->e.esi = buffer_seg; | |
87 | regs->e.edi = buffer_adr; | |
88 | BE_int86(0x10, regs, regs); | |
89 | memcpy(mode_info->mode_info_block, buffer, | |
90 | sizeof(struct vbe_mode_info)); | |
91 | mode_info->valid = true; | |
92 | ||
93 | vesa_mode |= (1 << 14); | |
94 | /* request clearing of framebuffer */ | |
95 | vesa_mode &= ~(1 << 15); | |
96 | regs->e.eax = VESA_SET_MODE; | |
97 | regs->e.ebx = vesa_mode; | |
98 | BE_int86(0x10, regs, regs); | |
99 | } | |
100 | ||
ece92f85 JJ |
101 | /**************************************************************************** |
102 | PARAMETERS: | |
9c7e4b06 | 103 | pcidev - PCI device info for the video card on the bus to boot |
4c59f953 | 104 | vga_info - BIOS emulator VGA info structure |
ece92f85 JJ |
105 | |
106 | REMARKS: | |
107 | This function executes the BIOS POST code on the controller. We assume that | |
108 | at this stage the controller has its I/O and memory space enabled and | |
109 | that all other controllers are in a disabled state. | |
110 | ****************************************************************************/ | |
4c59f953 SG |
111 | static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, |
112 | int vesa_mode, struct vbe_mode_info *mode_info) | |
ece92f85 JJ |
113 | { |
114 | RMREGS regs; | |
115 | RMSREGS sregs; | |
116 | ||
117 | /* Determine the value to store in AX for BIOS POST. Per the PCI specs, | |
118 | AH must contain the bus and AL must contain the devfn, encoded as | |
119 | (dev << 3) | fn | |
120 | */ | |
121 | memset(®s, 0, sizeof(regs)); | |
122 | memset(&sregs, 0, sizeof(sregs)); | |
123 | regs.x.ax = ((int)PCI_BUS(pcidev) << 8) | | |
124 | ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev); | |
125 | ||
126 | /*Setup the X86 emulator for the VGA BIOS*/ | |
4c59f953 | 127 | BE_setVGA(vga_info); |
ece92f85 JJ |
128 | |
129 | /*Execute the BIOS POST code*/ | |
130 | BE_callRealMode(0xC000, 0x0003, ®s, &sregs); | |
131 | ||
132 | /*Cleanup and exit*/ | |
4c59f953 SG |
133 | BE_getVGA(vga_info); |
134 | ||
135 | if (vesa_mode != -1) | |
136 | atibios_set_vesa_mode(®s, vesa_mode, mode_info); | |
ece92f85 JJ |
137 | } |
138 | ||
139 | /**************************************************************************** | |
140 | PARAMETERS: | |
9c7e4b06 WD |
141 | pcidev - PCI device info for the video card on the bus |
142 | bar - Place to return the base address register offset to use | |
ece92f85 JJ |
143 | |
144 | RETURNS: | |
145 | The address to use to map the secondary BIOS (AGP devices) | |
146 | ||
147 | REMARKS: | |
148 | Searches all the PCI base address registers for the device looking for a | |
149 | memory mapping that is large enough to hold our ROM BIOS. We usually end up | |
150 | finding the framebuffer mapping (usually BAR 0x10), and we use this mapping | |
151 | to map the BIOS for the device into. We use a mapping that is already | |
152 | assigned to the device to ensure the memory range will be passed through | |
153 | by any PCI->PCI or AGP->PCI bridge that may be present. | |
154 | ||
155 | NOTE: Usually this function is only used for AGP devices, but it may be | |
156 | used for PCI devices that have already been POST'ed and the BIOS | |
157 | ROM base address has been zero'ed out. | |
158 | ||
159 | NOTE: This function leaves the original memory aperture disabled by leaving | |
160 | it programmed to all 1's. It must be restored to the correct value | |
161 | later. | |
162 | ****************************************************************************/ | |
163 | static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar) | |
164 | { | |
165 | u32 base, size; | |
166 | ||
167 | for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) { | |
168 | pci_read_config_dword(pcidev, *bar, &base); | |
169 | if (!(base & 0x1)) { | |
170 | pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF); | |
171 | pci_read_config_dword(pcidev, *bar, &size); | |
172 | size = ~(size & ~0xFF) + 1; | |
173 | if (size >= MAX_BIOSLEN) | |
174 | return base & ~0xFF; | |
175 | } | |
176 | } | |
177 | return 0; | |
178 | } | |
179 | ||
180 | /**************************************************************************** | |
181 | REMARKS: | |
182 | Some non-x86 Linux kernels map PCI relocateable I/O to values that | |
183 | are above 64K, which will not work with the BIOS image that requires | |
184 | the offset for the I/O ports to be a maximum of 16-bits. Ideally | |
185 | someone should fix the kernel to map the I/O ports for VGA compatible | |
186 | devices to a different location (or just all I/O ports since it is | |
187 | unlikely you can have enough devices in the machine to use up all | |
188 | 64K of the I/O space - a total of more than 256 cards would be | |
189 | necessary). | |
190 | ||
191 | Anyway to fix this we change all I/O mapped base registers and | |
192 | chop off the top bits. | |
193 | ****************************************************************************/ | |
194 | static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base) | |
195 | { | |
196 | if ((*base & 0x1) && (*base > 0xFFFE)) { | |
197 | *base &= 0xFFFF; | |
198 | pci_write_config_dword(pcidev, reg, *base); | |
199 | ||
200 | } | |
201 | } | |
202 | ||
203 | /**************************************************************************** | |
204 | PARAMETERS: | |
9c7e4b06 | 205 | pcidev - PCI device info for the video card on the bus |
ece92f85 JJ |
206 | |
207 | RETURNS: | |
208 | Pointers to the mapped BIOS image | |
209 | ||
210 | REMARKS: | |
211 | Maps a pointer to the BIOS image on the graphics card on the PCI bus. | |
212 | ****************************************************************************/ | |
213 | void *PCI_mapBIOSImage(pci_dev_t pcidev) | |
214 | { | |
f6a7a2e8 | 215 | u32 BIOSImageBus; |
ece92f85 JJ |
216 | int BIOSImageBAR; |
217 | u8 *BIOSImage; | |
218 | ||
219 | /*Save PCI BAR registers that might get changed*/ | |
220 | pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress); | |
221 | pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10); | |
222 | pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); | |
223 | pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18); | |
224 | pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); | |
225 | ||
226 | /*Fix up I/O base registers to less than 64K */ | |
227 | if(saveBaseAddress14 != 0) | |
228 | PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); | |
229 | else | |
230 | PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); | |
231 | ||
232 | /* Some cards have problems that stop us from being able to read the | |
233 | BIOS image from the ROM BAR. To fix this we have to do some chipset | |
234 | specific programming for different cards to solve this problem. | |
9c7e4b06 | 235 | */ |
ece92f85 | 236 | |
f6a7a2e8 ES |
237 | BIOSImageBus = PCI_findBIOSAddr(pcidev, &BIOSImageBAR); |
238 | if (BIOSImageBus == 0) { | |
ece92f85 JJ |
239 | printf("Find bios addr error\n"); |
240 | return NULL; | |
241 | } | |
242 | ||
f6a7a2e8 ES |
243 | BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus, |
244 | PCI_REGION_MEM, 0, MAP_NOCACHE); | |
ece92f85 JJ |
245 | |
246 | /*Change the PCI BAR registers to map it onto the bus.*/ | |
247 | pci_write_config_dword(pcidev, BIOSImageBAR, 0); | |
f6a7a2e8 | 248 | pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); |
ece92f85 JJ |
249 | |
250 | udelay(1); | |
251 | ||
252 | /*Check that the BIOS image is valid. If not fail, or return the | |
253 | compiled in BIOS image if that option was enabled | |
254 | */ | |
255 | if (BIOSImage[0] != 0x55 || BIOSImage[1] != 0xAA || BIOSImage[2] == 0) { | |
256 | return NULL; | |
257 | } | |
258 | ||
259 | return BIOSImage; | |
260 | } | |
261 | ||
262 | /**************************************************************************** | |
263 | PARAMETERS: | |
9c7e4b06 | 264 | pcidev - PCI device info for the video card on the bus |
ece92f85 JJ |
265 | |
266 | REMARKS: | |
267 | Unmaps the BIOS image for the device and restores framebuffer mappings | |
268 | ****************************************************************************/ | |
269 | void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) | |
270 | { | |
271 | pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); | |
272 | pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10); | |
273 | pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14); | |
274 | pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); | |
275 | pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); | |
276 | } | |
277 | ||
278 | /**************************************************************************** | |
279 | PARAMETERS: | |
9c7e4b06 | 280 | pcidev - PCI device info for the video card on the bus to boot |
ece92f85 JJ |
281 | VGAInfo - BIOS emulator VGA info structure |
282 | ||
283 | RETURNS: | |
472d5460 | 284 | true if successfully initialised, false if not. |
ece92f85 JJ |
285 | |
286 | REMARKS: | |
287 | Loads and POST's the display controllers BIOS, directly from the BIOS | |
288 | image we can extract over the PCI bus. | |
289 | ****************************************************************************/ | |
4c59f953 SG |
290 | static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, |
291 | BE_VGAInfo *vga_info, int vesa_mode, | |
292 | struct vbe_mode_info *mode_info) | |
ece92f85 | 293 | { |
4c59f953 SG |
294 | u32 bios_image_len; |
295 | uchar *mapped_bios; | |
296 | uchar *copy_of_bios; | |
297 | ||
298 | if (bios_rom) { | |
299 | copy_of_bios = bios_rom; | |
300 | bios_image_len = bios_len; | |
301 | } else { | |
302 | /* | |
303 | * Allocate memory to store copy of BIOS from display | |
304 | * controller | |
305 | */ | |
306 | mapped_bios = PCI_mapBIOSImage(pcidev); | |
307 | if (mapped_bios == NULL) { | |
308 | printf("videoboot: Video ROM failed to map!\n"); | |
309 | return false; | |
310 | } | |
ece92f85 | 311 | |
4c59f953 | 312 | bios_image_len = mapped_bios[2] * 512; |
ece92f85 | 313 | |
4c59f953 SG |
314 | copy_of_bios = malloc(bios_image_len); |
315 | if (copy_of_bios == NULL) { | |
316 | printf("videoboot: Out of memory!\n"); | |
317 | return false; | |
318 | } | |
319 | memcpy(copy_of_bios, mapped_bios, bios_image_len); | |
320 | PCI_unmapBIOSImage(pcidev, mapped_bios); | |
ece92f85 | 321 | } |
ece92f85 | 322 | |
4c59f953 SG |
323 | /*Save information in vga_info structure*/ |
324 | vga_info->function = PCI_FUNC(pcidev); | |
325 | vga_info->device = PCI_DEV(pcidev); | |
326 | vga_info->bus = PCI_BUS(pcidev); | |
327 | vga_info->pcidev = pcidev; | |
328 | vga_info->BIOSImage = copy_of_bios; | |
329 | vga_info->BIOSImageLen = bios_image_len; | |
ece92f85 JJ |
330 | |
331 | /*Now execute the BIOS POST for the device*/ | |
4c59f953 | 332 | if (copy_of_bios[0] != 0x55 || copy_of_bios[1] != 0xAA) { |
ece92f85 JJ |
333 | printf("videoboot: Video ROM image is invalid!\n"); |
334 | return false; | |
335 | } | |
336 | ||
4c59f953 | 337 | PCI_doBIOSPOST(pcidev, vga_info, vesa_mode, mode_info); |
ece92f85 JJ |
338 | |
339 | /*Reset the size of the BIOS image to the final size*/ | |
4c59f953 | 340 | vga_info->BIOSImageLen = copy_of_bios[2] * 512; |
ece92f85 JJ |
341 | return true; |
342 | } | |
343 | ||
4c59f953 | 344 | int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop) |
ece92f85 JJ |
345 | { |
346 | BE_VGAInfo *VGAInfo; | |
347 | ||
348 | printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n", | |
349 | PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev)); | |
350 | ||
351 | /*Initialise the x86 BIOS emulator*/ | |
352 | if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) { | |
353 | printf("videoboot: Out of memory!\n"); | |
4c59f953 | 354 | return -ENOMEM; |
ece92f85 JJ |
355 | } |
356 | memset(VGAInfo, 0, sizeof(*VGAInfo)); | |
357 | BE_init(0, 65536, VGAInfo, 0); | |
4c59f953 | 358 | *vga_infop = VGAInfo; |
ece92f85 | 359 | |
4c59f953 SG |
360 | return 0; |
361 | } | |
ece92f85 | 362 | |
4c59f953 SG |
363 | void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)) |
364 | { | |
365 | X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func); | |
366 | } | |
367 | ||
368 | int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, | |
369 | BE_VGAInfo *vga_info, int clean_up, int vesa_mode, | |
370 | struct vbe_mode_info *mode_info) | |
371 | { | |
372 | /*Post all the display controller BIOS'es*/ | |
373 | if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info, | |
374 | vesa_mode, mode_info)) | |
375 | return -EINVAL; | |
376 | ||
377 | /* | |
378 | * Cleanup and exit the emulator if requested. If the BIOS emulator | |
379 | * is needed after booting the card, we will not call BE_exit and | |
380 | * leave it enabled for further use (ie: VESA driver etc). | |
ece92f85 | 381 | */ |
4c59f953 | 382 | if (clean_up) { |
ece92f85 | 383 | BE_exit(); |
4c59f953 SG |
384 | if (vga_info->BIOSImage) |
385 | free(vga_info->BIOSImage); | |
386 | free(vga_info); | |
387 | vga_info = NULL; | |
ece92f85 | 388 | } |
4c59f953 SG |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
393 | /**************************************************************************** | |
394 | PARAMETERS: | |
395 | pcidev - PCI device info for the video card on the bus to boot | |
396 | pVGAInfo - Place to return VGA info structure is requested | |
397 | cleanUp - true to clean up on exit, false to leave emulator active | |
398 | ||
399 | REMARKS: | |
400 | Boots the PCI/AGP video card on the bus using the Video ROM BIOS image | |
401 | and the X86 BIOS emulator module. | |
402 | ****************************************************************************/ | |
403 | int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up) | |
404 | { | |
405 | BE_VGAInfo *VGAInfo; | |
406 | int ret; | |
407 | ||
408 | ret = biosemu_setup(pcidev, &VGAInfo); | |
409 | if (ret) | |
410 | return false; | |
411 | ret = biosemu_run(pcidev, NULL, 0, VGAInfo, clean_up, -1, NULL); | |
412 | if (ret) | |
413 | return false; | |
414 | ||
415 | /* Return VGA info pointer if the caller requested it*/ | |
ece92f85 JJ |
416 | if (pVGAInfo) |
417 | *pVGAInfo = VGAInfo; | |
4c59f953 | 418 | |
ece92f85 JJ |
419 | return true; |
420 | } |