[u-boot.git] / arch / arm / cpu / arm925t / start.S

/*
 *  armboot - Startup Code for ARM925 CPU-core
 *
 *  Copyright (c) 2003  Texas Instruments
 *
 *  ----- Adapted for OMAP1510 from ARM920 code ------
 *
 *  Copyright (c) 2001	Marius Gröger <[email protected]>
 *  Copyright (c) 2002	Alex Züpke <[email protected]>
 *  Copyright (c) 2002	Gary Jennejohn <[email protected]>
 *  Copyright (c) 2003	Richard Woodruff <[email protected]>
 *  Copyright (c) 2003	Kshitij	 <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP1510)
#include <./configs/omap1510.h>
#endif

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:	b       reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end__ - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * Set up 925T mode
	 */
	mov r1, #0x81               /* Set ARM925T configuration. */
	mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */

	/*
	 * turn off the watchdog, unlock/diable sequence
	 */
	mov  r1, #0xF5
	ldr  r0, =WDTIM_MODE
	strh r1, [r0]
	mov  r1, #0xA0
	strh r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov r1, #0xffffffff
	ldr r0, =REG_IHL1_MIR
	str r1, [r0]
	ldr r0, =REG_IHL2_MIR
	str r1, [r0]

	/*
	 * wait for dpll to lock
	 */
	ldr  r0, =CK_DPLL1
	mov  r1, #0x10
	strh r1, [r0]
poll1:
	ldrh r1, [r0]
	ands r1, r1, #0x01
	beq poll1

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl  cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	mov	pc, lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * Go setup Memory and board specific bits prior to relocation.
	 */
	mov	ip, lr          /* perserve link reg across call */
	bl	lowlevel_init   /* go setup pll,mux,memory */
	mov	lr, ip          /* restore link */
	mov	pc, lr          /* back to my caller */
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12

	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp                          @ save current stack into r0 (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
	str     lr, [r8, #0]                    @ Save calling PC
	mrs     r6, spsr
	str     r6, [r8, #4]                    @ Save CPSR
	str     r0, [r8, #8]                    @ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN

	str	lr, [r13]			@ save caller lr in position 0 of saved stack
	mrs	lr, spsr                        @ get the spsr
	str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13                       @ switch modes, make sure moves will execute
	mov	lr, pc                          @ capture return pc
	movs	pc, lr                          @ jump to next instruction & switch modes.
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

	.align	5
.globl reset_cpu
reset_cpu:
	ldr	r1, rstctl1     /* get clkm1 reset ctl */
	mov     r3, #0x3	/* dsp_en + arm_rst = global reset */
	strh	r3, [r1]        /* force reset */
	mov	r0, r0
_loop_forever:
	b	_loop_forever
rstctl1:
	.word	0xfffece10
Commit	Line	Data
2e5983d2 WD	1	/*
	2	* armboot - Startup Code for ARM925 CPU-core
	3	*
	4	* Copyright (c) 2003 Texas Instruments
	5	*
	6	* ----- Adapted for OMAP1510 from ARM920 code ------
	7	*
fa82f871 AA	8	* Copyright (c) 2001 Marius Gröger <[email protected]>
fa82f871 AA	9	* Copyright (c) 2002 Alex Züpke <[email protected]>
792a09eb	10	* Copyright (c) 2002 Gary Jennejohn <[email protected]>
2e5983d2	11	* Copyright (c) 2003 Richard Woodruff <[email protected]>
53677ef1	12	* Copyright (c) 2003 Kshitij <[email protected]>
2e5983d2 WD	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32
25ddd1fb	33	#include <asm-offsets.h>
2e5983d2 WD	34	#include <config.h>
	35	#include <version.h>
	36
	37	#if defined(CONFIG_OMAP1510)
	38	#include <./configs/omap1510.h>
	39	#endif
	40
	41	/*
	42	*************************************************************************
	43	*
	44	* Jump vector table as in table 3.1 in [1]
	45	*
	46	*************************************************************************
	47	*/
	48
	49
	50	.globl _start
	51	_start: b reset
	52	ldr pc, _undefined_instruction
	53	ldr pc, _software_interrupt
	54	ldr pc, _prefetch_abort
	55	ldr pc, _data_abort
	56	ldr pc, _not_used
	57	ldr pc, _irq
	58	ldr pc, _fiq
	59
	60	_undefined_instruction: .word undefined_instruction
	61	_software_interrupt: .word software_interrupt
	62	_prefetch_abort: .word prefetch_abort
	63	_data_abort: .word data_abort
	64	_not_used: .word not_used
	65	_irq: .word irq
	66	_fiq: .word fiq
	67
	68	.balignl 16,0xdeadbeef
	69
	70
	71	/*
	72	*************************************************************************
	73	*
	74	* Startup Code (reset vector)
	75	*
	76	* do important init only if we don't start from memory!
	77	* setup Memory and board specific bits prior to relocation.
	78	* relocate armboot to ram
	79	* setup stack
	80	*
	81	*************************************************************************
	82	*/
	83
405d023b	84	.globl _TEXT_BASE
2e5983d2	85	_TEXT_BASE:
14d0a02a	86	.word CONFIG_SYS_TEXT_BASE
2e5983d2	87
2e5983d2	88	/*
f6e20fc6	89	* These are defined in the board-specific linker script.
3336ca60 AA	90	* Subtracting _start from them lets the linker put their
	91	* relative position in the executable instead of leaving
	92	* them null.
2e5983d2	93	*/
3336ca60 AA	94	.globl _bss_start_ofs
	95	_bss_start_ofs:
	96	.word __bss_start - _start
f6e20fc6	97
3336ca60 AA	98	.globl _bss_end_ofs
3336ca60 AA	99	_bss_end_ofs:
44c6e659	100	.word __bss_end__ - _start
2e5983d2	101
f326cbba PYC	102	.globl _end_ofs
	103	_end_ofs:
	104	.word _end - _start
	105
2e5983d2 WD	106	#ifdef CONFIG_USE_IRQ
	107	/* IRQ stack memory (calculated at run-time) */
	108	.globl IRQ_STACK_START
	109	IRQ_STACK_START:
	110	.word 0x0badc0de
	111
	112	/* IRQ stack memory (calculated at run-time) */
	113	.globl FIQ_STACK_START
	114	FIQ_STACK_START:
	115	.word 0x0badc0de
	116	#endif
	117
405d023b HS	118	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	119	.globl IRQ_STACK_START_IN
	120	IRQ_STACK_START_IN:
	121	.word 0x0badc0de
	122
405d023b HS	123	/*
	124	* the actual reset code
	125	*/
	126
	127	reset:
	128	/*
	129	* set the cpu to SVC32 mode
	130	*/
	131	mrs r0,cpsr
	132	bic r0,r0,#0x1f
	133	orr r0,r0,#0xd3
	134	msr cpsr,r0
	135
	136	/*
	137	* Set up 925T mode
	138	*/
	139	mov r1, #0x81 /* Set ARM925T configuration. */
	140	mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */
	141
	142	/*
	143	* turn off the watchdog, unlock/diable sequence
	144	*/
	145	mov r1, #0xF5
	146	ldr r0, =WDTIM_MODE
	147	strh r1, [r0]
	148	mov r1, #0xA0
	149	strh r1, [r0]
	150
	151	/*
	152	* mask all IRQs by setting all bits in the INTMR - default
	153	*/
	154	mov r1, #0xffffffff
	155	ldr r0, =REG_IHL1_MIR
	156	str r1, [r0]
	157	ldr r0, =REG_IHL2_MIR
	158	str r1, [r0]
	159
	160	/*
	161	* wait for dpll to lock
	162	*/
	163	ldr r0, =CK_DPLL1
	164	mov r1, #0x10
	165	strh r1, [r0]
	166	poll1:
	167	ldrh r1, [r0]
	168	ands r1, r1, #0x01
	169	beq poll1
	170
	171	/*
	172	* we do sys-critical inits only at reboot,
	173	* not when booting from ram!
	174	*/
	175	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	176	bl cpu_init_crit
	177	#endif
	178
e05e5de7	179	bl _main
405d023b HS	180
	181	/------------------------------------------------------------------------------/
	182
	183	/*
	184	* void relocate_code (addr_sp, gd, addr_moni)
	185	*
	186	* This "function" does not return, instead it continues in RAM
	187	* after relocating the monitor code.
	188	*
	189	*/
	190	.globl relocate_code
	191	relocate_code:
	192	mov r4, r0 /* save addr_sp */
	193	mov r5, r1 /* save addr of gd */
	194	mov r6, r2 /* save addr of destination */
405d023b	195
405d023b	196	adr r0, _start
a1a47d3c	197	cmp r0, r6
76abfa57	198	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
e05e5de7	199	beq relocate_done /* skip relocation */
a78fb68f	200	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	201	ldr r3, _bss_start_ofs
3336ca60 AA	202	add r2, r0, r3 /* r2 <- source end address */
405d023b	203
405d023b HS	204	copy_loop:
405d023b HS	205	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	206	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	207	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	208	blo copy_loop
405d023b	209
401bb30b	210	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	211	/*
	212	* fix .rel.dyn relocations
	213	*/
	214	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	215	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	216	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	217	add r10, r10, r0 /* r10 <- sym table in FLASH */
	218	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	219	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	220	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	221	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
405d023b	222	fixloop:
3336ca60 AA	223	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	224	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	225	ldr r1, [r2, #4]
1f52d89f AB	226	and r7, r1, #0xff
1f52d89f AB	227	cmp r7, #23 /* relative fixup? */
3336ca60	228	beq fixrel
1f52d89f	229	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	230	beq fixabs
	231	/* ignore unknown type of fixup */
	232	b fixnext
	233	fixabs:
	234	/* absolute fix: set location to (offset) symbol value */
	235	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	236	add r1, r10, r1 /* r1 <- address of symbol in table */
	237	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	238	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	239	b fixnext
	240	fixrel:
	241	/* relative fix: increase location by offset */
	242	ldr r1, [r0]
	243	add r1, r1, r9
	244	fixnext:
	245	str r1, [r0]
	246	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
405d023b	247	cmp r2, r3
79e63139	248	blo fixloop
405d023b	249	#endif
405d023b	250
e05e5de7	251	relocate_done:
405d023b	252
405d023b HS	253	mov pc, lr
405d023b HS	254
3336ca60 AA	255	_rel_dyn_start_ofs:
	256	.word __rel_dyn_start - _start
	257	_rel_dyn_end_ofs:
	258	.word __rel_dyn_end - _start
	259	_dynsym_start_ofs:
	260	.word __dynsym_start - _start
	261
e05e5de7 AA	262	.globl c_runtime_cpu_setup
	263	c_runtime_cpu_setup:
	264
	265	mov pc, lr
	266
2e5983d2 WD	267	/*
	268	*************************************************************************
	269	*
	270	* CPU_init_critical registers
	271	*
	272	* setup important registers
	273	* setup memory timing
	274	*
	275	*************************************************************************
	276	*/
	277
	278
	279	cpu_init_crit:
	280	/*
	281	* flush v4 I/D caches
	282	*/
	283	mov r0, #0
	284	mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
	285	mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
	286
	287	/*
	288	* disable MMU stuff and caches
	289	*/
	290	mrc p15, 0, r0, c1, c0, 0
	291	bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
	292	bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
	293	orr r0, r0, #0x00000002 @ set bit 2 (A) Align
	294	orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
	295	mcr p15, 0, r0, c1, c0, 0
	296
	297	/*
	298	* Go setup Memory and board specific bits prior to relocation.
	299	*/
	300	mov ip, lr /* perserve link reg across call */
87cb6862	301	bl lowlevel_init /* go setup pll,mux,memory */
2e5983d2 WD	302	mov lr, ip /* restore link */
	303	mov pc, lr /* back to my caller */
	304	/*
	305	*************************************************************************
	306	*
	307	* Interrupt handling
	308	*
	309	*************************************************************************
	310	*/
	311
	312	@
	313	@ IRQ stack frame.
	314	@
	315	#define S_FRAME_SIZE 72
	316
	317	#define S_OLD_R0 68
	318	#define S_PSR 64
	319	#define S_PC 60
	320	#define S_LR 56
	321	#define S_SP 52
	322
	323	#define S_IP 48
	324	#define S_FP 44
	325	#define S_R10 40
	326	#define S_R9 36
	327	#define S_R8 32
	328	#define S_R7 28
	329	#define S_R6 24
	330	#define S_R5 20
	331	#define S_R4 16
	332	#define S_R3 12
	333	#define S_R2 8
	334	#define S_R1 4
	335	#define S_R0 0
	336
	337	#define MODE_SVC 0x13
	338	#define I_BIT 0x80
	339
	340	/*
	341	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	342	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	343	*/
	344
	345	.macro bad_save_user_regs
	346	sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
	347	stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
	348
405d023b	349	ldr r2, IRQ_STACK_START_IN
2e5983d2 WD	350	ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
	351	add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
	352
	353	add r5, sp, #S_SP
	354	mov r1, lr
	355	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
	356	mov r0, sp @ save current stack into r0 (param register)
	357	.endm
	358
	359	.macro irq_save_user_regs
	360	sub sp, sp, #S_FRAME_SIZE
	361	stmia sp, {r0 - r12} @ Calling r0-r12
	362	add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	363	stmdb r8, {sp, lr}^ @ Calling SP, LR
	364	str lr, [r8, #0] @ Save calling PC
	365	mrs r6, spsr
	366	str r6, [r8, #4] @ Save CPSR
	367	str r0, [r8, #8] @ Save OLD_R0
	368	mov r0, sp
	369	.endm
	370
	371	.macro irq_restore_user_regs
	372	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	373	mov r0, r0
	374	ldr lr, [sp, #S_PC] @ Get PC
	375	add sp, sp, #S_FRAME_SIZE
	376	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	377	.endm
	378
	379	.macro get_bad_stack
405d023b	380	ldr r13, IRQ_STACK_START_IN
2e5983d2 WD	381
	382	str lr, [r13] @ save caller lr in position 0 of saved stack
	383	mrs lr, spsr @ get the spsr
	384	str lr, [r13, #4] @ save spsr in position 1 of saved stack
	385
	386	mov r13, #MODE_SVC @ prepare SVC-Mode
	387	@ msr spsr_c, r13
	388	msr spsr, r13 @ switch modes, make sure moves will execute
	389	mov lr, pc @ capture return pc
	390	movs pc, lr @ jump to next instruction & switch modes.
	391	.endm
	392
	393	.macro get_irq_stack @ setup IRQ stack
	394	ldr sp, IRQ_STACK_START
	395	.endm
	396
	397	.macro get_fiq_stack @ setup FIQ stack
	398	ldr sp, FIQ_STACK_START
	399	.endm
	400
	401	/*
	402	* exception handlers
	403	*/
	404	.align 5
	405	undefined_instruction:
	406	get_bad_stack
	407	bad_save_user_regs
53677ef1	408	bl do_undefined_instruction
2e5983d2 WD	409
	410	.align 5
	411	software_interrupt:
	412	get_bad_stack
	413	bad_save_user_regs
53677ef1	414	bl do_software_interrupt
2e5983d2 WD	415
	416	.align 5
	417	prefetch_abort:
	418	get_bad_stack
	419	bad_save_user_regs
53677ef1	420	bl do_prefetch_abort
2e5983d2 WD	421
	422	.align 5
	423	data_abort:
	424	get_bad_stack
	425	bad_save_user_regs
53677ef1	426	bl do_data_abort
2e5983d2 WD	427
	428	.align 5
	429	not_used:
	430	get_bad_stack
	431	bad_save_user_regs
53677ef1	432	bl do_not_used
2e5983d2 WD	433
	434	#ifdef CONFIG_USE_IRQ
	435
	436	.align 5
	437	irq:
	438	get_irq_stack
	439	irq_save_user_regs
53677ef1	440	bl do_irq
2e5983d2 WD	441	irq_restore_user_regs
	442
	443	.align 5
	444	fiq:
	445	get_fiq_stack
	446	/* someone ought to write a more effiction fiq_save_user_regs */
	447	irq_save_user_regs
53677ef1	448	bl do_fiq
2e5983d2 WD	449	irq_restore_user_regs
	450
	451	#else
	452
	453	.align 5
	454	irq:
	455	get_bad_stack
	456	bad_save_user_regs
53677ef1	457	bl do_irq
2e5983d2 WD	458
	459	.align 5
	460	fiq:
	461	get_bad_stack
	462	bad_save_user_regs
53677ef1	463	bl do_fiq
2e5983d2 WD	464
	465	#endif
	466
	467	.align 5
	468	.globl reset_cpu
	469	reset_cpu:
	470	ldr r1, rstctl1 /* get clkm1 reset ctl */
1f4bb37d WD	471	mov r3, #0x3 /* dsp_en + arm_rst = global reset */
	472	strh r3, [r1] /* force reset */
	473	mov r0, r0
2e5983d2 WD	474	_loop_forever:
	475	b _loop_forever
	476	rstctl1:
	477	.word 0xfffece10