[u-boot.git] / arch / arm / cpu / arm720t / start.S

/*
 *  armboot - Startup Code for ARM720 CPU-core
 *
 *  Copyright (c) 2001	Marius Gröger <[email protected]>
 *  Copyright (c) 2002	Alex Züpke <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/hardware.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start: b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt:	.word _software_interrupt
_prefetch_abort:	.word _prefetch_abort
_data_abort:		.word _data_abort
_not_used:		.word _not_used
_irq:			.word _irq
_fiq:			.word _fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#endif	/* CONFIG_SPL_BUILD */

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from RAM!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
#ifdef CONFIG_SPL_BUILD
	.word	CONFIG_SPL_TEXT_BASE
#else
	.word	CONFIG_SYS_TEXT_BASE
#endif

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end__ - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	mov	pc, lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */

cpu_init_crit:

#if !defined(CONFIG_TEGRA)
	mov	ip, lr
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependent, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	bl	lowlevel_init
	mov	lr, ip
#endif

	mov	pc, lr


#ifndef CONFIG_SPL_BUILD
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC

	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^			@ Calling SP, LR
	str	lr, [r8, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]			@ Save CPSR
	str	r0, [r8, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str	lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* armboot - Startup Code for ARM720 CPU-core
	3	*
fa82f871 AA	4	* Copyright (c) 2001 Marius Gröger <[email protected]>
fa82f871 AA	5	* Copyright (c) 2002 Alex Züpke <[email protected]>
fe8c2806 WD	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
cdc7fea1	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
fe8c2806 WD	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
25ddd1fb	26	#include <asm-offsets.h>
fe8c2806 WD	27	#include <config.h>
fe8c2806 WD	28	#include <version.h>
39539887	29	#include <asm/hardware.h>
fe8c2806 WD	30
	31	/*
	32	*************************************************************************
	33	*
	34	* Jump vector table as in table 3.1 in [1]
	35	*
	36	*************************************************************************
	37	*/
	38
	39
	40	.globl _start
cdc7fea1	41	_start: b reset
fe8c2806 WD	42	ldr pc, _undefined_instruction
	43	ldr pc, _software_interrupt
	44	ldr pc, _prefetch_abort
	45	ldr pc, _data_abort
	46	ldr pc, _not_used
	47	ldr pc, _irq
	48	ldr pc, _fiq
	49
c7da6c67 AM	50	#ifdef CONFIG_SPL_BUILD
	51	_undefined_instruction: .word _undefined_instruction
	52	_software_interrupt: .word _software_interrupt
	53	_prefetch_abort: .word _prefetch_abort
	54	_data_abort: .word _data_abort
	55	_not_used: .word _not_used
	56	_irq: .word _irq
	57	_fiq: .word _fiq
c037c93b	58	_pad: .word 0x12345678 /* now 164=64 /
c7da6c67	59	#else
cdc7fea1	60	_undefined_instruction: .word undefined_instruction
fe8c2806 WD	61	_software_interrupt: .word software_interrupt
	62	_prefetch_abort: .word prefetch_abort
	63	_data_abort: .word data_abort
	64	_not_used: .word not_used
	65	_irq: .word irq
	66	_fiq: .word fiq
c037c93b	67	_pad: .word 0x12345678 /* now 164=64 /
c7da6c67	68	#endif /* CONFIG_SPL_BUILD */
fe8c2806 WD	69
	70	.balignl 16,0xdeadbeef
	71
	72
	73	/*
	74	*************************************************************************
	75	*
	76	* Startup Code (reset vector)
	77	*
f6e20fc6	78	* do important init only if we don't start from RAM!
fe8c2806 WD	79	* relocate armboot to ram
	80	* setup stack
	81	* jump to second stage
	82	*
	83	*************************************************************************
	84	*/
	85
abef7b85	86	.globl _TEXT_BASE
fe8c2806	87	_TEXT_BASE:
c037c93b AM	88	#ifdef CONFIG_SPL_BUILD
	89	.word CONFIG_SPL_TEXT_BASE
	90	#else
14d0a02a	91	.word CONFIG_SYS_TEXT_BASE
c037c93b	92	#endif
fe8c2806	93
fe8c2806	94	/*
f6e20fc6	95	* These are defined in the board-specific linker script.
3336ca60 AA	96	* Subtracting _start from them lets the linker put their
	97	* relative position in the executable instead of leaving
	98	* them null.
fe8c2806	99	*/
3336ca60 AA	100	.globl _bss_start_ofs
	101	_bss_start_ofs:
	102	.word __bss_start - _start
f6e20fc6	103
3336ca60 AA	104	.globl _bss_end_ofs
3336ca60 AA	105	_bss_end_ofs:
44c6e659	106	.word __bss_end__ - _start
fe8c2806	107
f326cbba PYC	108	.globl _end_ofs
	109	_end_ofs:
	110	.word _end - _start
	111
fe8c2806 WD	112	#ifdef CONFIG_USE_IRQ
	113	/* IRQ stack memory (calculated at run-time) */
	114	.globl IRQ_STACK_START
	115	IRQ_STACK_START:
	116	.word 0x0badc0de
	117
	118	/* IRQ stack memory (calculated at run-time) */
	119	.globl FIQ_STACK_START
	120	FIQ_STACK_START:
	121	.word 0x0badc0de
	122	#endif
	123
abef7b85 HS	124	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	125	.globl IRQ_STACK_START_IN
	126	IRQ_STACK_START_IN:
	127	.word 0x0badc0de
	128
abef7b85 HS	129	/*
	130	* the actual reset code
	131	*/
	132
	133	reset:
	134	/*
	135	* set the cpu to SVC32 mode
	136	*/
	137	mrs r0,cpsr
	138	bic r0,r0,#0x1f
	139	orr r0,r0,#0xd3
	140	msr cpsr,r0
	141
	142	/*
	143	* we do sys-critical inits only at reboot,
	144	* not when booting from ram!
	145	*/
	146	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	147	bl cpu_init_crit
	148	#endif
	149
e05e5de7	150	bl _main
abef7b85 HS	151
	152	/------------------------------------------------------------------------------/
	153
	154	/*
	155	* void relocate_code (addr_sp, gd, addr_moni)
	156	*
	157	* This "function" does not return, instead it continues in RAM
	158	* after relocating the monitor code.
	159	*
	160	*/
	161	.globl relocate_code
	162	relocate_code:
	163	mov r4, r0 /* save addr_sp */
	164	mov r5, r1 /* save addr of gd */
	165	mov r6, r2 /* save addr of destination */
abef7b85	166
abef7b85	167	adr r0, _start
a1a47d3c	168	cmp r0, r6
c7da6c67	169	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
e05e5de7	170	beq relocate_done /* skip relocation */
a78fb68f	171	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	172	ldr r3, _bss_start_ofs
3336ca60 AA	173	add r2, r0, r3 /* r2 <- source end address */
abef7b85	174
abef7b85 HS	175	copy_loop:
abef7b85 HS	176	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	177	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	178	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	179	blo copy_loop
abef7b85	180
401bb30b	181	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	182	/*
	183	* fix .rel.dyn relocations
	184	*/
	185	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	186	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	187	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	188	add r10, r10, r0 /* r10 <- sym table in FLASH */
	189	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	190	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	191	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	192	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
abef7b85	193	fixloop:
3336ca60 AA	194	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	195	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	196	ldr r1, [r2, #4]
1f52d89f AB	197	and r7, r1, #0xff
1f52d89f AB	198	cmp r7, #23 /* relative fixup? */
3336ca60	199	beq fixrel
1f52d89f	200	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	201	beq fixabs
	202	/* ignore unknown type of fixup */
	203	b fixnext
	204	fixabs:
	205	/* absolute fix: set location to (offset) symbol value */
	206	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	207	add r1, r10, r1 /* r1 <- address of symbol in table */
	208	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	209	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	210	b fixnext
	211	fixrel:
	212	/* relative fix: increase location by offset */
	213	ldr r1, [r0]
	214	add r1, r1, r9
	215	fixnext:
	216	str r1, [r0]
	217	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
abef7b85	218	cmp r2, r3
79e63139	219	blo fixloop
abef7b85	220	#endif
abef7b85	221
e05e5de7	222	relocate_done:
abef7b85	223
abef7b85 HS	224	mov pc, lr
abef7b85 HS	225
3336ca60 AA	226	_rel_dyn_start_ofs:
	227	.word __rel_dyn_start - _start
	228	_rel_dyn_end_ofs:
	229	.word __rel_dyn_end - _start
	230	_dynsym_start_ofs:
	231	.word __dynsym_start - _start
abef7b85	232
e05e5de7 AA	233	.globl c_runtime_cpu_setup
	234	c_runtime_cpu_setup:
	235
	236	mov pc, lr
	237
fe8c2806 WD	238	/*
	239	*************************************************************************
	240	*
	241	* CPU_init_critical registers
	242	*
	243	* setup important registers
	244	* setup memory timing
	245	*
	246	*************************************************************************
	247	*/
	248
fe8c2806	249	cpu_init_crit:
fe8c2806	250
6f62f420	251	#if !defined(CONFIG_TEGRA)
87cb6862	252	mov ip, lr
fe8c2806 WD	253	/*
fe8c2806 WD	254	* before relocating, we have to setup RAM timing
f6e20fc6	255	* because memory timing is board-dependent, you will
400558b5	256	* find a lowlevel_init.S in your board directory.
fe8c2806	257	*/
400558b5	258	bl lowlevel_init
fe8c2806	259	mov lr, ip
6bd2447e	260	#endif
fe8c2806 WD	261
	262	mov pc, lr
	263
	264
c7da6c67	265	#ifndef CONFIG_SPL_BUILD
fe8c2806 WD	266	/*
	267	*************************************************************************
	268	*
	269	* Interrupt handling
	270	*
	271	*************************************************************************
	272	*/
	273
	274	@
	275	@ IRQ stack frame.
	276	@
	277	#define S_FRAME_SIZE 72
	278
	279	#define S_OLD_R0 68
	280	#define S_PSR 64
	281	#define S_PC 60
	282	#define S_LR 56
	283	#define S_SP 52
	284
	285	#define S_IP 48
	286	#define S_FP 44
	287	#define S_R10 40
	288	#define S_R9 36
	289	#define S_R8 32
	290	#define S_R7 28
	291	#define S_R6 24
	292	#define S_R5 20
	293	#define S_R4 16
	294	#define S_R3 12
	295	#define S_R2 8
	296	#define S_R1 4
	297	#define S_R0 0
	298
	299	#define MODE_SVC 0x13
	300	#define I_BIT 0x80
	301
	302	/*
	303	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	304	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	305	*/
	306
	307	.macro bad_save_user_regs
	308	sub sp, sp, #S_FRAME_SIZE
	309	stmia sp, {r0 - r12} @ Calling r0-r12
cdc7fea1	310	add r8, sp, #S_PC
fe8c2806	311
abef7b85	312	ldr r2, IRQ_STACK_START_IN
cdc7fea1	313	ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
fe8c2806 WD	314	add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
	315
	316	add r5, sp, #S_SP
	317	mov r1, lr
cdc7fea1	318	stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
fe8c2806 WD	319	mov r0, sp
	320	.endm
	321
	322	.macro irq_save_user_regs
	323	sub sp, sp, #S_FRAME_SIZE
	324	stmia sp, {r0 - r12} @ Calling r0-r12
cdc7fea1 WD	325	add r8, sp, #S_PC
	326	stmdb r8, {sp, lr}^ @ Calling SP, LR
	327	str lr, [r8, #0] @ Save calling PC
	328	mrs r6, spsr
	329	str r6, [r8, #4] @ Save CPSR
	330	str r0, [r8, #8] @ Save OLD_R0
fe8c2806 WD	331	mov r0, sp
	332	.endm
	333
	334	.macro irq_restore_user_regs
	335	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	336	mov r0, r0
	337	ldr lr, [sp, #S_PC] @ Get PC
	338	add sp, sp, #S_FRAME_SIZE
	339	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	340	.endm
	341
	342	.macro get_bad_stack
abef7b85	343	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
fe8c2806 WD	344
	345	str lr, [r13] @ save caller lr / spsr
	346	mrs lr, spsr
cdc7fea1	347	str lr, [r13, #4]
fe8c2806 WD	348
	349	mov r13, #MODE_SVC @ prepare SVC-Mode
	350	msr spsr_c, r13
	351	mov lr, pc
	352	movs pc, lr
	353	.endm
	354
	355	.macro get_irq_stack @ setup IRQ stack
	356	ldr sp, IRQ_STACK_START
	357	.endm
	358
	359	.macro get_fiq_stack @ setup FIQ stack
	360	ldr sp, FIQ_STACK_START
	361	.endm
	362
	363	/*
	364	* exception handlers
	365	*/
cdc7fea1	366	.align 5
fe8c2806 WD	367	undefined_instruction:
	368	get_bad_stack
	369	bad_save_user_regs
cdc7fea1	370	bl do_undefined_instruction
fe8c2806 WD	371
	372	.align 5
	373	software_interrupt:
	374	get_bad_stack
	375	bad_save_user_regs
cdc7fea1	376	bl do_software_interrupt
fe8c2806 WD	377
	378	.align 5
	379	prefetch_abort:
	380	get_bad_stack
	381	bad_save_user_regs
cdc7fea1	382	bl do_prefetch_abort
fe8c2806 WD	383
	384	.align 5
	385	data_abort:
	386	get_bad_stack
	387	bad_save_user_regs
cdc7fea1	388	bl do_data_abort
fe8c2806 WD	389
	390	.align 5
	391	not_used:
	392	get_bad_stack
	393	bad_save_user_regs
cdc7fea1	394	bl do_not_used
fe8c2806 WD	395
	396	#ifdef CONFIG_USE_IRQ
	397
	398	.align 5
	399	irq:
	400	get_irq_stack
	401	irq_save_user_regs
cdc7fea1	402	bl do_irq
fe8c2806 WD	403	irq_restore_user_regs
	404
	405	.align 5
	406	fiq:
	407	get_fiq_stack
	408	/* someone ought to write a more effiction fiq_save_user_regs */
	409	irq_save_user_regs
cdc7fea1	410	bl do_fiq
fe8c2806 WD	411	irq_restore_user_regs
	412
	413	#else
	414
	415	.align 5
	416	irq:
	417	get_bad_stack
	418	bad_save_user_regs
cdc7fea1	419	bl do_irq
fe8c2806 WD	420
	421	.align 5
	422	fiq:
	423	get_bad_stack
	424	bad_save_user_regs
cdc7fea1	425	bl do_fiq
fe8c2806 WD	426
fe8c2806 WD	427	#endif
c7da6c67	428	#endif /* CONFIG_SPL_BUILD */