[u-boot.git] / arch / arm / cpu / arm1136 / start.S

/*
 *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
 *
 *  Copyright (c) 2004	Texas Instruments <[email protected]>
 *
 *  Copyright (c) 2001	Marius Gröger <[email protected]>
 *  Copyright (c) 2002	Alex Züpke <[email protected]>
 *  Copyright (c) 2002	Gary Jennejohn <[email protected]>
 *  Copyright (c) 2003	Richard Woodruff <[email protected]>
 *  Copyright (c) 2003	Kshitij <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.globl _start
_start: b	reset
#ifdef CONFIG_SPL_BUILD
	ldr	pc, _hang
	ldr	pc, _hang
	ldr	pc, _hang
	ldr	pc, _hang
	ldr	pc, _hang
	ldr	pc, _hang
	ldr	pc, _hang

_hang:
	.word	do_hang
	.word	0x12345678
	.word	0x12345678
	.word	0x12345678
	.word	0x12345678
	.word	0x12345678
	.word	0x12345678
	.word	0x12345678	/* now 16*4=64 */
#else
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
#endif	/* CONFIG_SPL_BUILD */
.global _end_vect
_end_vect:

	.balignl 16,0xdeadbeef
/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.global	_image_copy_end_ofs
_image_copy_end_ofs:
	.word 	__image_copy_end - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end__ - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

#ifdef CONFIG_OMAP2420H4
       /* Copy vectors to mask ROM indirect addr */
	adr	r0, _start		/* r0 <- current position of code   */
		add     r0, r0, #4				/* skip reset vector			*/
	mov	r2, #64			/* r2 <- size to copy  */
	add	r2, r0, r2		/* r2 <- source end address	    */
	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
	mov	r3, #SRAM_OFFSET1
	add	r1, r1, r3
	mov	r3, #SRAM_OFFSET2
	add	r1, r1, r3
next:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	bne	next			/* loop until equal */
	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
#endif
	/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl  cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _image_copy_end_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
	bx	lr

#endif

relocate_done:

	bx	lr

#ifndef CONFIG_SPL_BUILD

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

#endif

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	bx	lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * Jump to board specific initialization... The Mask ROM will have already initialized
	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
	 */
	mov	ip, lr		/* persevere link reg across call */
	bl	lowlevel_init	/* go setup pll,mux,memory */
	mov	lr, ip		/* restore link */
	mov	pc, lr		/* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

#ifndef CONFIG_SPL_BUILD
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12

	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp				@ save current stack into r0 (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	stmdb	r8, {sp, lr}^			@ Calling SP, LR
	str	lr, [r8, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]			@ Save CPSR
	str	r0, [r8, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)

	str	lr, [r13]			@ save caller lr in position 0 of saved stack
	mrs	lr, spsr			@ get the spsr
	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13			@ switch modes, make sure moves will execute
	mov	lr, pc				@ capture return pc
	movs	pc, lr				@ jump to next instruction & switch modes.
	.endm

	.macro get_bad_stack_swi
	sub	r13, r13, #4			@ space on current stack for scratch reg.
	str	r0, [r13]			@ save R0's value.
	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
	str	lr, [r0]			@ save caller lr in position 0 of saved stack
	mrs	r0, spsr			@ get the spsr
	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
	ldr	r0, [r13]			@ restore r0
	add	r13, r13, #4			@ pop stack entry
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm
#endif	/* CONFIG_SPL_BUILD */

/*
 * exception handlers
 */
#ifdef CONFIG_SPL_BUILD
	.align	5
do_hang:
	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
	bl	hang				/* hang and never return */
#else	/* !CONFIG_SPL_BUILD */
	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack_swi
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif
	.align 5
.global arm1136_cache_flush
arm1136_cache_flush:
#if !defined(CONFIG_SYS_ICACHE_OFF)
		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
#endif
#if !defined(CONFIG_SYS_DCACHE_OFF)
		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
#endif
		mov	pc, lr			@ back to caller
#endif	/* CONFIG_SPL_BUILD */
Commit	Line	Data
8ed96046 WD	1	/*
	2	* armboot - Startup Code for OMP2420/ARM1136 CPU-core
	3	*
082acfd4	4	* Copyright (c) 2004 Texas Instruments <[email protected]>
8ed96046	5	*
fa82f871 AA	6	* Copyright (c) 2001 Marius Gröger <[email protected]>
fa82f871 AA	7	* Copyright (c) 2002 Alex Züpke <[email protected]>
792a09eb	8	* Copyright (c) 2002 Gary Jennejohn <[email protected]>
8ed96046 WD	9	* Copyright (c) 2003 Richard Woodruff <[email protected]>
	10	* Copyright (c) 2003 Kshitij <[email protected]>
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
082acfd4	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8ed96046 WD	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
25ddd1fb	31	#include <asm-offsets.h>
8ed96046 WD	32	#include <config.h>
8ed96046 WD	33	#include <version.h>
8ed96046	34	.globl _start
082acfd4	35	_start: b reset
401bb30b	36	#ifdef CONFIG_SPL_BUILD
751b9b51 KP	37	ldr pc, _hang
	38	ldr pc, _hang
	39	ldr pc, _hang
	40	ldr pc, _hang
	41	ldr pc, _hang
	42	ldr pc, _hang
	43	ldr pc, _hang
	44
	45	_hang:
	46	.word do_hang
	47	.word 0x12345678
	48	.word 0x12345678
	49	.word 0x12345678
	50	.word 0x12345678
	51	.word 0x12345678
	52	.word 0x12345678
	53	.word 0x12345678 /* now 164=64 /
	54	#else
8ed96046 WD	55	ldr pc, _undefined_instruction
	56	ldr pc, _software_interrupt
	57	ldr pc, _prefetch_abort
	58	ldr pc, _data_abort
	59	ldr pc, _not_used
	60	ldr pc, _irq
	61	ldr pc, _fiq
	62
082acfd4	63	_undefined_instruction: .word undefined_instruction
8ed96046 WD	64	_software_interrupt: .word software_interrupt
	65	_prefetch_abort: .word prefetch_abort
	66	_data_abort: .word data_abort
	67	_not_used: .word not_used
	68	_irq: .word irq
	69	_fiq: .word fiq
082acfd4	70	_pad: .word 0x12345678 /* now 164=64 /
401bb30b	71	#endif /* CONFIG_SPL_BUILD */
8ed96046 WD	72	.global _end_vect
	73	_end_vect:
	74
	75	.balignl 16,0xdeadbeef
	76	/*
	77	*************************************************************************
	78	*
	79	* Startup Code (reset vector)
	80	*
	81	* do important init only if we don't start from memory!
	82	* setup Memory and board specific bits prior to relocation.
	83	* relocate armboot to ram
	84	* setup stack
	85	*
	86	*************************************************************************
	87	*/
	88
e48b7c0a	89	.globl _TEXT_BASE
8ed96046	90	_TEXT_BASE:
14d0a02a	91	.word CONFIG_SYS_TEXT_BASE
8ed96046	92
8ed96046 WD	93	/*
8ed96046 WD	94	* These are defined in the board-specific linker script.
bafe7437 HS	95	* Subtracting _start from them lets the linker put their
	96	* relative position in the executable instead of leaving
	97	* them null.
8ed96046	98	*/
bafe7437 HS	99	.globl _bss_start_ofs
	100	_bss_start_ofs:
	101	.word __bss_start - _start
e48b7c0a	102
b736e4b9 SB	103	.global _image_copy_end_ofs
	104	_image_copy_end_ofs:
	105	.word __image_copy_end - _start
	106
bafe7437 HS	107	.globl _bss_end_ofs
bafe7437 HS	108	_bss_end_ofs:
44c6e659	109	.word __bss_end__ - _start
e48b7c0a	110
f326cbba PYC	111	.globl _end_ofs
	112	_end_ofs:
	113	.word _end - _start
	114
8ed96046 WD	115	#ifdef CONFIG_USE_IRQ
	116	/* IRQ stack memory (calculated at run-time) */
	117	.globl IRQ_STACK_START
	118	IRQ_STACK_START:
	119	.word 0x0badc0de
	120
	121	/* IRQ stack memory (calculated at run-time) */
	122	.globl FIQ_STACK_START
	123	FIQ_STACK_START:
	124	.word 0x0badc0de
	125	#endif
	126
e48b7c0a HS	127	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	128	.globl IRQ_STACK_START_IN
	129	IRQ_STACK_START_IN:
	130	.word 0x0badc0de
e48b7c0a	131
e48b7c0a HS	132	/*
	133	* the actual reset code
	134	*/
	135
	136	reset:
	137	/*
	138	* set the cpu to SVC32 mode
	139	*/
	140	mrs r0,cpsr
	141	bic r0,r0,#0x1f
	142	orr r0,r0,#0xd3
	143	msr cpsr,r0
	144
	145	#ifdef CONFIG_OMAP2420H4
	146	/* Copy vectors to mask ROM indirect addr */
	147	adr r0, _start /* r0 <- current position of code */
	148	add r0, r0, #4 /* skip reset vector */
	149	mov r2, #64 /* r2 <- size to copy */
	150	add r2, r0, r2 /* r2 <- source end address */
	151	mov r1, #SRAM_OFFSET0 /* build vect addr */
	152	mov r3, #SRAM_OFFSET1
	153	add r1, r1, r3
	154	mov r3, #SRAM_OFFSET2
	155	add r1, r1, r3
	156	next:
	157	ldmia r0!, {r3-r10} /* copy from source address [r0] */
	158	stmia r1!, {r3-r10} /* copy to target address [r1] */
	159	cmp r0, r2 /* until source end address [r2] */
	160	bne next /* loop until equal */
	161	bl cpy_clk_code /* put dpll adjust code behind vectors */
	162	#endif
	163	/* the mask ROM code should have PLL and others stable */
	164	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	165	bl cpu_init_crit
	166	#endif
	167
e05e5de7	168	bl _main
e48b7c0a HS	169
	170	/------------------------------------------------------------------------------/
	171
	172	/*
	173	* void relocate_code (addr_sp, gd, addr_moni)
	174	*
	175	* This "function" does not return, instead it continues in RAM
	176	* after relocating the monitor code.
	177	*
	178	*/
	179	.globl relocate_code
	180	relocate_code:
	181	mov r4, r0 /* save addr_sp */
	182	mov r5, r1 /* save addr of gd */
	183	mov r6, r2 /* save addr of destination */
e48b7c0a	184
e48b7c0a	185	adr r0, _start
a1a47d3c	186	cmp r0, r6
76abfa57	187	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
e05e5de7	188	beq relocate_done /* skip relocation */
a78fb68f	189	mov r1, r6 /* r1 <- scratch for copy_loop */
b736e4b9	190	ldr r3, _image_copy_end_ofs
bafe7437	191	add r2, r0, r3 /* r2 <- source end address */
e48b7c0a	192
e48b7c0a HS	193	copy_loop:
e48b7c0a HS	194	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	195	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	196	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	197	blo copy_loop
e48b7c0a	198
401bb30b	199	#ifndef CONFIG_SPL_BUILD
bafe7437 HS	200	/*
	201	* fix .rel.dyn relocations
	202	*/
	203	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	204	sub r9, r6, r0 /* r9 <- relocation offset */
bafe7437 HS	205	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	206	add r10, r10, r0 /* r10 <- sym table in FLASH */
	207	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	208	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	209	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	210	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
e48b7c0a	211	fixloop:
8c0c2b90 GR	212	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
8c0c2b90 GR	213	add r0, r0, r9 /* r0 <- location to fix up in RAM */
bafe7437	214	ldr r1, [r2, #4]
1f52d89f AB	215	and r7, r1, #0xff
1f52d89f AB	216	cmp r7, #23 /* relative fixup? */
bafe7437	217	beq fixrel
1f52d89f	218	cmp r7, #2 /* absolute fixup? */
bafe7437 HS	219	beq fixabs
	220	/* ignore unknown type of fixup */
	221	b fixnext
	222	fixabs:
	223	/* absolute fix: set location to (offset) symbol value */
	224	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	225	add r1, r10, r1 /* r1 <- address of symbol in table */
	226	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	227	add r1, r1, r9 /* r1 <- relocated sym addr */
bafe7437 HS	228	b fixnext
	229	fixrel:
	230	/* relative fix: increase location by offset */
	231	ldr r1, [r0]
	232	add r1, r1, r9
	233	fixnext:
	234	str r1, [r0]
8c0c2b90	235	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
e48b7c0a	236	cmp r2, r3
79e63139	237	blo fixloop
e05e5de7 AA	238	bx lr
	239
	240	#endif
	241
	242	relocate_done:
	243
	244	bx lr
	245
	246	#ifndef CONFIG_SPL_BUILD
b736e4b9 SB	247
	248	_rel_dyn_start_ofs:
	249	.word __rel_dyn_start - _start
	250	_rel_dyn_end_ofs:
	251	.word __rel_dyn_end - _start
	252	_dynsym_start_ofs:
	253	.word __dynsym_start - _start
e48b7c0a	254
b736e4b9	255	#endif
428f7188	256
e05e5de7 AA	257	.globl c_runtime_cpu_setup
e05e5de7 AA	258	c_runtime_cpu_setup:
e48b7c0a	259
e05e5de7	260	bx lr
bafe7437	261
8ed96046 WD	262	/*
	263	*************************************************************************
	264	*
	265	* CPU_init_critical registers
	266	*
	267	* setup important registers
	268	* setup memory timing
	269	*
	270	*************************************************************************
	271	*/
40c642bc	272	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
8ed96046 WD	273	cpu_init_crit:
	274	/*
	275	* flush v4 I/D caches
	276	*/
	277	mov r0, #0
409a07c9 GD	278	mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
409a07c9 GD	279	mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
8ed96046 WD	280
	281	/*
	282	* disable MMU stuff and caches
	283	*/
	284	mrc p15, 0, r0, c1, c0, 0
	285	bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
	286	bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
	287	orr r0, r0, #0x00000002 @ set bit 2 (A) Align
8ed96046	288	orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
8ed96046 WD	289	mcr p15, 0, r0, c1, c0, 0
	290
	291	/*
082acfd4 WD	292	* Jump to board specific initialization... The Mask ROM will have already initialized
082acfd4 WD	293	* basic memory. Go here to bump up clock rate and handle wake up conditions.
8ed96046	294	*/
082acfd4	295	mov ip, lr /* persevere link reg across call */
87cb6862	296	bl lowlevel_init /* go setup pll,mux,memory */
082acfd4 WD	297	mov lr, ip /* restore link */
082acfd4 WD	298	mov pc, lr /* back to my caller */
40c642bc	299	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
751b9b51	300
401bb30b	301	#ifndef CONFIG_SPL_BUILD
8ed96046 WD	302	/*
	303	*************************************************************************
	304	*
	305	* Interrupt handling
	306	*
	307	*************************************************************************
	308	*/
	309	@
	310	@ IRQ stack frame.
	311	@
	312	#define S_FRAME_SIZE 72
	313
	314	#define S_OLD_R0 68
	315	#define S_PSR 64
	316	#define S_PC 60
	317	#define S_LR 56
	318	#define S_SP 52
	319
	320	#define S_IP 48
	321	#define S_FP 44
	322	#define S_R10 40
	323	#define S_R9 36
	324	#define S_R8 32
	325	#define S_R7 28
	326	#define S_R6 24
	327	#define S_R5 20
	328	#define S_R4 16
	329	#define S_R3 12
	330	#define S_R2 8
	331	#define S_R1 4
	332	#define S_R0 0
	333
	334	#define MODE_SVC 0x13
	335	#define I_BIT 0x80
	336
	337	/*
	338	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	339	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	340	*/
	341
	342	.macro bad_save_user_regs
082acfd4	343	sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
8ed96046 WD	344	stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
8ed96046 WD	345
e48b7c0a	346	ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
082acfd4	347	ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
8ed96046 WD	348	add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
	349
	350	add r5, sp, #S_SP
	351	mov r1, lr
082acfd4 WD	352	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
082acfd4 WD	353	mov r0, sp @ save current stack into r0 (param register)
8ed96046 WD	354	.endm
	355
	356	.macro irq_save_user_regs
	357	sub sp, sp, #S_FRAME_SIZE
	358	stmia sp, {r0 - r12} @ Calling r0-r12
082acfd4 WD	359	add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	360	stmdb r8, {sp, lr}^ @ Calling SP, LR
	361	str lr, [r8, #0] @ Save calling PC
	362	mrs r6, spsr
	363	str r6, [r8, #4] @ Save CPSR
	364	str r0, [r8, #8] @ Save OLD_R0
8ed96046 WD	365	mov r0, sp
	366	.endm
	367
	368	.macro irq_restore_user_regs
	369	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	370	mov r0, r0
	371	ldr lr, [sp, #S_PC] @ Get PC
	372	add sp, sp, #S_FRAME_SIZE
	373	subs pc, lr, #4 @ return & move spsr_svc into cpsr
	374	.endm
	375
	376	.macro get_bad_stack
e48b7c0a	377	ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
8ed96046 WD	378
8ed96046 WD	379	str lr, [r13] @ save caller lr in position 0 of saved stack
082acfd4 WD	380	mrs lr, spsr @ get the spsr
082acfd4 WD	381	str lr, [r13, #4] @ save spsr in position 1 of saved stack
8ed96046 WD	382
	383	mov r13, #MODE_SVC @ prepare SVC-Mode
	384	@ msr spsr_c, r13
082acfd4 WD	385	msr spsr, r13 @ switch modes, make sure moves will execute
	386	mov lr, pc @ capture return pc
	387	movs pc, lr @ jump to next instruction & switch modes.
8ed96046 WD	388	.endm
	389
	390	.macro get_bad_stack_swi
082acfd4 WD	391	sub r13, r13, #4 @ space on current stack for scratch reg.
082acfd4 WD	392	str r0, [r13] @ save R0's value.
e48b7c0a	393	ldr r0, IRQ_STACK_START_IN @ get data regions start
8ed96046	394	str lr, [r0] @ save caller lr in position 0 of saved stack
082acfd4 WD	395	mrs r0, spsr @ get the spsr
	396	str lr, [r0, #4] @ save spsr in position 1 of saved stack
	397	ldr r0, [r13] @ restore r0
	398	add r13, r13, #4 @ pop stack entry
8ed96046 WD	399	.endm
	400
	401	.macro get_irq_stack @ setup IRQ stack
	402	ldr sp, IRQ_STACK_START
	403	.endm
	404
	405	.macro get_fiq_stack @ setup FIQ stack
	406	ldr sp, FIQ_STACK_START
	407	.endm
401bb30b	408	#endif /* CONFIG_SPL_BUILD */
8ed96046 WD	409
	410	/*
	411	* exception handlers
	412	*/
401bb30b	413	#ifdef CONFIG_SPL_BUILD
751b9b51 KP	414	.align 5
	415	do_hang:
	416	ldr sp, _TEXT_BASE /* use 32 words about stack */
	417	bl hang /* hang and never return */
401bb30b	418	#else /* !CONFIG_SPL_BUILD */
082acfd4	419	.align 5
8ed96046 WD	420	undefined_instruction:
	421	get_bad_stack
	422	bad_save_user_regs
082acfd4	423	bl do_undefined_instruction
8ed96046 WD	424
	425	.align 5
	426	software_interrupt:
	427	get_bad_stack_swi
	428	bad_save_user_regs
082acfd4	429	bl do_software_interrupt
8ed96046 WD	430
	431	.align 5
	432	prefetch_abort:
	433	get_bad_stack
	434	bad_save_user_regs
082acfd4	435	bl do_prefetch_abort
8ed96046 WD	436
	437	.align 5
	438	data_abort:
	439	get_bad_stack
	440	bad_save_user_regs
082acfd4	441	bl do_data_abort
8ed96046 WD	442
	443	.align 5
	444	not_used:
	445	get_bad_stack
	446	bad_save_user_regs
082acfd4	447	bl do_not_used
8ed96046 WD	448
	449	#ifdef CONFIG_USE_IRQ
	450
	451	.align 5
	452	irq:
	453	get_irq_stack
	454	irq_save_user_regs
082acfd4	455	bl do_irq
8ed96046 WD	456	irq_restore_user_regs
	457
	458	.align 5
	459	fiq:
	460	get_fiq_stack
	461	/* someone ought to write a more effiction fiq_save_user_regs */
	462	irq_save_user_regs
082acfd4	463	bl do_fiq
8ed96046 WD	464	irq_restore_user_regs
	465
	466	#else
	467
	468	.align 5
	469	irq:
	470	get_bad_stack
	471	bad_save_user_regs
082acfd4	472	bl do_irq
8ed96046 WD	473
	474	.align 5
	475	fiq:
	476	get_bad_stack
	477	bad_save_user_regs
082acfd4	478	bl do_fiq
8ed96046 WD	479
	480	#endif
	481	.align 5
	482	.global arm1136_cache_flush
	483	arm1136_cache_flush:
e47f2db5	484	#if !defined(CONFIG_SYS_ICACHE_OFF)
8ed96046	485	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
7e4a9e6d	486	#endif
e47f2db5	487	#if !defined(CONFIG_SYS_DCACHE_OFF)
7e4a9e6d HS	488	mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
7e4a9e6d HS	489	#endif
8ed96046	490	mov pc, lr @ back to caller
401bb30b	491	#endif /* CONFIG_SPL_BUILD */