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1 | /* |
2 | * Configuation settings for the SAMA5D3xEK board. | |
3 | * | |
4 | * Copyright (C) 2012 - 2013 Atmel | |
5 | * | |
6 | * based on at91sam9m10g45ek.h by: | |
7 | * Stelian Pop <[email protected]> | |
8 | * Lead Tech Design <www.leadtechdesign.com> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
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11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
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16 | /* |
17 | * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH | |
18 | * before the common header. | |
19 | */ | |
20 | #include "at91-sama5_common.h" | |
3225f34e | 21 | |
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22 | #define CONFIG_BOARD_LATE_INIT |
23 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
24 | ||
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25 | /* serial console */ |
26 | #define CONFIG_ATMEL_USART | |
27 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
28 | #define CONFIG_USART_ID ATMEL_ID_DBGU | |
29 | ||
30 | /* | |
31 | * This needs to be defined for the OHCI code to work but it is defined as | |
32 | * ATMEL_ID_UHPHS in the CPU specific header files. | |
33 | */ | |
34 | #define ATMEL_ID_UHP ATMEL_ID_UHPHS | |
35 | ||
36 | /* | |
37 | * Specify the clock enable bit in the PMC_SCER register. | |
38 | */ | |
39 | #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP | |
40 | ||
41 | /* LCD */ | |
42 | #define CONFIG_LCD | |
43 | #define LCD_BPP LCD_COLOR16 | |
44 | #define LCD_OUTPUT_BPP 24 | |
45 | #define CONFIG_LCD_LOGO | |
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46 | #define CONFIG_LCD_INFO |
47 | #define CONFIG_LCD_INFO_BELOW_LOGO | |
48 | #define CONFIG_SYS_WHITE_ON_BLACK | |
49 | #define CONFIG_ATMEL_HLCD | |
50 | #define CONFIG_ATMEL_LCD_RGB565 | |
51 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
52 | ||
53 | /* board specific (not enough SRAM) */ | |
54 | #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 | |
55 | ||
d6b79434 | 56 | /* NOR flash */ |
b2d387bc | 57 | #ifndef CONFIG_SYS_NO_FLASH |
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58 | #define CONFIG_FLASH_CFI_DRIVER |
59 | #define CONFIG_SYS_FLASH_CFI | |
60 | #define CONFIG_SYS_FLASH_PROTECTION | |
61 | #define CONFIG_SYS_FLASH_BASE 0x10000000 | |
62 | #define CONFIG_SYS_MAX_FLASH_SECT 131 | |
63 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
d6b79434 | 64 | #endif |
3225f34e | 65 | |
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66 | /* SDRAM */ |
67 | #define CONFIG_NR_DRAM_BANKS 1 | |
68 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS | |
69 | #define CONFIG_SYS_SDRAM_SIZE 0x20000000 | |
70 | ||
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71 | #ifdef CONFIG_SPL_BUILD |
72 | #define CONFIG_SYS_INIT_SP_ADDR 0x310000 | |
73 | #else | |
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74 | #define CONFIG_SYS_INIT_SP_ADDR \ |
75 | (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) | |
c5e8885a | 76 | #endif |
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77 | |
78 | /* SerialFlash */ | |
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79 | |
80 | #ifdef CONFIG_CMD_SF | |
81 | #define CONFIG_ATMEL_SPI | |
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82 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
83 | #endif | |
84 | ||
85 | /* NAND flash */ | |
86 | #define CONFIG_CMD_NAND | |
87 | ||
88 | #ifdef CONFIG_CMD_NAND | |
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89 | #define CONFIG_NAND_ATMEL |
90 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
91 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 | |
92 | /* our ALE is AD21 */ | |
93 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
94 | /* our CLE is AD22 */ | |
95 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
96 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
97 | /* PMECC & PMERRLOC */ | |
98 | #define CONFIG_ATMEL_NAND_HWECC | |
99 | #define CONFIG_ATMEL_NAND_HW_PMECC | |
100 | #define CONFIG_PMECC_CAP 4 | |
101 | #define CONFIG_PMECC_SECTOR_SIZE 512 | |
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102 | #define CONFIG_CMD_NAND_TRIMFFS |
103 | #endif | |
104 | ||
105 | /* Ethernet Hardware */ | |
106 | #define CONFIG_MACB | |
107 | #define CONFIG_RMII | |
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108 | #define CONFIG_NET_RETRY_COUNT 20 |
109 | #define CONFIG_MACB_SEARCH_PHY | |
e08d6f3a | 110 | #define CONFIG_RGMII |
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111 | #define CONFIG_PHYLIB |
112 | #define CONFIG_PHY_MICREL | |
113 | #define CONFIG_PHY_MICREL_KSZ9021 | |
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114 | |
115 | /* MMC */ | |
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116 | |
117 | #ifdef CONFIG_CMD_MMC | |
118 | #define CONFIG_MMC | |
119 | #define CONFIG_GENERIC_MMC | |
120 | #define CONFIG_GENERIC_ATMEL_MCI | |
121 | #define ATMEL_BASE_MMCI ATMEL_BASE_MCI0 | |
122 | #endif | |
123 | ||
124 | /* USB */ | |
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125 | |
126 | #ifdef CONFIG_CMD_USB | |
127 | #define CONFIG_USB_ATMEL | |
dcd2f1a0 | 128 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
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129 | #define CONFIG_USB_OHCI_NEW |
130 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
131 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI | |
132 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" | |
133 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 | |
134 | #define CONFIG_DOS_PARTITION | |
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135 | #endif |
136 | ||
3668ce3c | 137 | /* USB device */ |
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138 | #define CONFIG_USB_ETHER |
139 | #define CONFIG_USB_ETH_RNDIS | |
140 | #define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK" | |
141 | ||
3225f34e | 142 | #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) |
a248558a | 143 | #define CONFIG_FAT_WRITE |
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144 | #endif |
145 | ||
146 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ | |
147 | ||
148 | #ifdef CONFIG_SYS_USE_SERIALFLASH | |
7a53b954 | 149 | /* override the bootcmd, bootargs and other configuration for spi flash env*/ |
3225f34e | 150 | #elif CONFIG_SYS_USE_NANDFLASH |
dc018fef | 151 | /* override the bootcmd, bootargs and other configuration nandflash env */ |
3225f34e | 152 | #elif CONFIG_SYS_USE_MMC |
372ca03f | 153 | /* override the bootcmd, bootargs and other configuration for sd/mmc env */ |
3225f34e | 154 | #else |
a4c79b3a | 155 | #define CONFIG_ENV_IS_NOWHERE |
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156 | #endif |
157 | ||
c5e8885a | 158 | /* SPL */ |
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159 | #define CONFIG_SPL_FRAMEWORK |
160 | #define CONFIG_SPL_TEXT_BASE 0x300000 | |
161 | #define CONFIG_SPL_MAX_SIZE 0x10000 | |
162 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 | |
163 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
164 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 | |
165 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 | |
166 | ||
c5e8885a | 167 | #define CONFIG_SPL_BOARD_INIT |
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168 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
169 | ||
c5e8885a | 170 | #ifdef CONFIG_SYS_USE_MMC |
993ea97e | 171 | #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds |
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172 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 |
173 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 | |
e2ccdf89 | 174 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 175 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
8a45b0ba | 176 | |
27019e4a | 177 | #elif CONFIG_SYS_USE_NANDFLASH |
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178 | #define CONFIG_SPL_NAND_DRIVERS |
179 | #define CONFIG_SPL_NAND_BASE | |
180 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 | |
181 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
182 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 | |
183 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
184 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
185 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 | |
186 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 | |
e166a831 | 187 | #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER |
27019e4a | 188 | |
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189 | #elif CONFIG_SYS_USE_SERIALFLASH |
190 | #define CONFIG_SPL_SPI_SUPPORT | |
191 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
192 | #define CONFIG_SPL_SPI_LOAD | |
7a53b954 | 193 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 |
8a45b0ba | 194 | |
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195 | #endif |
196 | ||
3225f34e | 197 | #endif |