[u-boot.git] / drivers / net / dwmac_socfpga.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018 Marek Vasut <[email protected]>
 *
 * Altera SoCFPGA EMAC extras
 */

#include <common.h>
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
#include <phy.h>
#include <regmap.h>
#include <reset.h>
#include <syscon.h>
#include "designware.h"
#include <dm/device_compat.h>
#include <linux/err.h>

#include <asm/arch/system_manager.h>

struct dwmac_socfpga_platdata {
	struct dw_eth_pdata	dw_eth_pdata;
	void			*phy_intf;
	u32			reg_shift;
};

static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
{
	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
	struct regmap *regmap;
	struct ofnode_phandle_args args;
	void *range;
	int ret;

	ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
					 2, 0, &args);
	if (ret) {
		dev_err(dev, "Failed to get syscon: %d\n", ret);
		return ret;
	}

	if (args.args_count != 2) {
		dev_err(dev, "Invalid number of syscon args\n");
		return -EINVAL;
	}

	regmap = syscon_node_to_regmap(args.node);
	if (IS_ERR(regmap)) {
		ret = PTR_ERR(regmap);
		dev_err(dev, "Failed to get regmap: %d\n", ret);
		return ret;
	}

	range = regmap_get_range(regmap, 0);
	if (!range) {
		dev_err(dev, "Failed to get regmap range\n");
		return -ENOMEM;
	}

	pdata->phy_intf = range + args.args[0];
	pdata->reg_shift = args.args[1];

	return designware_eth_ofdata_to_platdata(dev);
}

static int dwmac_socfpga_probe(struct udevice *dev)
{
	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
	struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
	struct reset_ctl_bulk reset_bulk;
	int ret;
	u32 modereg;
	u32 modemask;

	switch (edata->phy_interface) {
	case PHY_INTERFACE_MODE_MII:
	case PHY_INTERFACE_MODE_GMII:
		modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
		break;
	case PHY_INTERFACE_MODE_RMII:
		modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
		break;
	case PHY_INTERFACE_MODE_RGMII:
		modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
		break;
	default:
		dev_err(dev, "Unsupported PHY mode\n");
		return -EINVAL;
	}

	ret = reset_get_bulk(dev, &reset_bulk);
	if (ret) {
		dev_err(dev, "Failed to get reset: %d\n", ret);
		return ret;
	}

	reset_assert_bulk(&reset_bulk);

	modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
	clrsetbits_le32(pdata->phy_intf, modemask,
			modereg << pdata->reg_shift);

	reset_release_bulk(&reset_bulk);

	return designware_eth_probe(dev);
}

static const struct udevice_id dwmac_socfpga_ids[] = {
	{ .compatible = "altr,socfpga-stmmac" },
	{ }
};

U_BOOT_DRIVER(dwmac_socfpga) = {
	.name		= "dwmac_socfpga",
	.id		= UCLASS_ETH,
	.of_match	= dwmac_socfpga_ids,
	.ofdata_to_platdata = dwmac_socfpga_ofdata_to_platdata,
	.probe		= dwmac_socfpga_probe,
	.ops		= &designware_eth_ops,
	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
	.platdata_auto_alloc_size = sizeof(struct dwmac_socfpga_platdata),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
215a0656 MV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018 Marek Vasut <[email protected]>
	4	*
	5	* Altera SoCFPGA EMAC extras
	6	*/
	7
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <dm.h>
	11	#include <clk.h>
	12	#include <phy.h>
	13	#include <regmap.h>
	14	#include <reset.h>
	15	#include <syscon.h>
	16	#include "designware.h"
336d4615	17	#include <dm/device_compat.h>
61b29b82	18	#include <linux/err.h>
215a0656 MV	19
	20	#include <asm/arch/system_manager.h>
	21
215a0656 MV	22	struct dwmac_socfpga_platdata {
215a0656 MV	23	struct dw_eth_pdata dw_eth_pdata;
215a0656	24	void *phy_intf;
4f1267ce	25	u32 reg_shift;
215a0656 MV	26	};
	27
	28	static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
	29	{
	30	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
	31	struct regmap *regmap;
	32	struct ofnode_phandle_args args;
	33	void *range;
	34	int ret;
	35
	36	ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
	37	2, 0, &args);
	38	if (ret) {
	39	dev_err(dev, "Failed to get syscon: %d\n", ret);
	40	return ret;
	41	}
	42
	43	if (args.args_count != 2) {
	44	dev_err(dev, "Invalid number of syscon args\n");
	45	return -EINVAL;
	46	}
	47
	48	regmap = syscon_node_to_regmap(args.node);
	49	if (IS_ERR(regmap)) {
	50	ret = PTR_ERR(regmap);
	51	dev_err(dev, "Failed to get regmap: %d\n", ret);
	52	return ret;
	53	}
	54
	55	range = regmap_get_range(regmap, 0);
	56	if (!range) {
	57	dev_err(dev, "Failed to get regmap range\n");
	58	return -ENOMEM;
	59	}
	60
	61	pdata->phy_intf = range + args.args[0];
4f1267ce	62	pdata->reg_shift = args.args[1];
215a0656 MV	63
	64	return designware_eth_ofdata_to_platdata(dev);
	65	}
	66
	67	static int dwmac_socfpga_probe(struct udevice *dev)
	68	{
	69	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
	70	struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
	71	struct reset_ctl_bulk reset_bulk;
	72	int ret;
4f1267ce SG	73	u32 modereg;
	74	u32 modemask;
	75
	76	switch (edata->phy_interface) {
	77	case PHY_INTERFACE_MODE_MII:
	78	case PHY_INTERFACE_MODE_GMII:
	79	modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	80	break;
	81	case PHY_INTERFACE_MODE_RMII:
	82	modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
	83	break;
	84	case PHY_INTERFACE_MODE_RGMII:
	85	modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
	86	break;
	87	default:
	88	dev_err(dev, "Unsupported PHY mode\n");
	89	return -EINVAL;
215a0656 MV	90	}
215a0656 MV	91
4f1267ce SG	92	ret = reset_get_bulk(dev, &reset_bulk);
	93	if (ret) {
	94	dev_err(dev, "Failed to get reset: %d\n", ret);
	95	return ret;
	96	}
	97
	98	reset_assert_bulk(&reset_bulk);
	99
	100	modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
	101	clrsetbits_le32(pdata->phy_intf, modemask,
	102	modereg << pdata->reg_shift);
	103
	104	reset_release_bulk(&reset_bulk);
	105
215a0656 MV	106	return designware_eth_probe(dev);
	107	}
	108
	109	static const struct udevice_id dwmac_socfpga_ids[] = {
	110	{ .compatible = "altr,socfpga-stmmac" },
	111	{ }
	112	};
	113
	114	U_BOOT_DRIVER(dwmac_socfpga) = {
	115	.name = "dwmac_socfpga",
	116	.id = UCLASS_ETH,
	117	.of_match = dwmac_socfpga_ids,
	118	.ofdata_to_platdata = dwmac_socfpga_ofdata_to_platdata,
	119	.probe = dwmac_socfpga_probe,
	120	.ops = &designware_eth_ops,
	121	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
	122	.platdata_auto_alloc_size = sizeof(struct dwmac_socfpga_platdata),
	123	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	124	};