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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
1f045217 | 2 | /* |
385c9ef5 HS |
3 | * Copyright (C) 2009 Sergey Kubushyn <[email protected]> |
4 | * Copyright (C) 2009 - 2013 Heiko Schocher <[email protected]> | |
5 | * Changes for multibus/multiadapter I2C support. | |
6 | * | |
1f045217 WD |
7 | * (C) Copyright 2001 |
8 | * Gerald Van Baren, Custom IDEAS, [email protected]. | |
9 | * | |
1f045217 WD |
10 | * The original I2C interface was |
11 | * (C) 2000 by Paolo Scaffardi ([email protected]) | |
12 | * AIRVENT SAM s.p.a - RIMINI(ITALY) | |
13 | * but has been changed substantially. | |
14 | */ | |
15 | ||
16 | #ifndef _I2C_H_ | |
17 | #define _I2C_H_ | |
18 | ||
f7ae49fc SG |
19 | #include <linker_lists.h> |
20 | ||
c6202d85 SG |
21 | /* |
22 | * For now there are essentially two parts to this file - driver model | |
69d9eda4 | 23 | * here at the top, and the older code below (with CONFIG_SYS_I2C_LEGACY being |
c6202d85 SG |
24 | * most recent). The plan is to migrate everything to driver model. |
25 | * The driver model structures and API are separate as they are different | |
26 | * enough as to be incompatible for compilation purposes. | |
27 | */ | |
28 | ||
c6202d85 SG |
29 | enum dm_i2c_chip_flags { |
30 | DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */ | |
31 | DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */ | |
32 | DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */ | |
33 | }; | |
34 | ||
7bd21b62 SG |
35 | /** enum i2c_speed_mode - standard I2C speed modes */ |
36 | enum i2c_speed_mode { | |
37 | IC_SPEED_MODE_STANDARD, | |
38 | IC_SPEED_MODE_FAST, | |
39 | IC_SPEED_MODE_FAST_PLUS, | |
40 | IC_SPEED_MODE_HIGH, | |
41 | IC_SPEED_MODE_FAST_ULTRA, | |
42 | ||
43 | IC_SPEED_MODE_COUNT, | |
44 | }; | |
45 | ||
46 | /** enum i2c_speed_rate - standard I2C speeds in Hz */ | |
47 | enum i2c_speed_rate { | |
48 | I2C_SPEED_STANDARD_RATE = 100000, | |
49 | I2C_SPEED_FAST_RATE = 400000, | |
50 | I2C_SPEED_FAST_PLUS_RATE = 1000000, | |
51 | I2C_SPEED_HIGH_RATE = 3400000, | |
52 | I2C_SPEED_FAST_ULTRA_RATE = 5000000, | |
53 | }; | |
54 | ||
55 | /** enum i2c_address_mode - available address modes */ | |
56 | enum i2c_address_mode { | |
57 | I2C_MODE_7_BIT, | |
58 | I2C_MODE_10_BIT | |
59 | }; | |
60 | ||
fd42f263 SG |
61 | /** enum i2c_device_t - Types of I2C devices, used for compatible strings */ |
62 | enum i2c_device_t { | |
63 | I2C_DEVICE_GENERIC, | |
64 | I2C_DEVICE_HID_OVER_I2C, | |
65 | }; | |
66 | ||
fffff726 | 67 | struct udevice; |
c6202d85 SG |
68 | /** |
69 | * struct dm_i2c_chip - information about an i2c chip | |
70 | * | |
71 | * An I2C chip is a device on the I2C bus. It sits at a particular address | |
72 | * and normally supports 7-bit or 10-bit addressing. | |
73 | * | |
caa4daa2 | 74 | * To obtain this structure, use dev_get_parent_plat(dev) where dev is |
e6f66ec0 | 75 | * the chip to examine. |
c6202d85 SG |
76 | * |
77 | * @chip_addr: Chip address on bus | |
78 | * @offset_len: Length of offset in bytes. A single byte offset can | |
79 | * represent up to 256 bytes. A value larger than 1 may be | |
80 | * needed for larger devices. | |
81 | * @flags: Flags for this chip (dm_i2c_chip_flags) | |
85968522 RB |
82 | * @chip_addr_offset_mask: Mask of offset bits within chip_addr. Used for |
83 | * devices which steal addresses as part of offset. | |
84 | * If offset_len is zero, then the offset is encoded | |
85 | * completely within the chip address itself. | |
86 | * e.g. a devce with chip address of 0x2c with 512 | |
87 | * registers might use the bottom bit of the address | |
88 | * to indicate which half of the address space is being | |
89 | * accessed while still only using 1 byte offset. | |
90 | * This means it will respond to chip address 0x2c and | |
91 | * 0x2d. | |
92 | * A real world example is the Atmel AT24C04. It's | |
93 | * datasheet explains it's usage of this addressing | |
94 | * mode. | |
c6202d85 | 95 | * @emul: Emulator for this chip address (only used for emulation) |
728d04cc SG |
96 | * @emul_idx: Emulator index, used for of-platdata and set by each i2c chip's |
97 | * bind() method. This allows i2c_emul_find() to work with of-platdata. | |
c6202d85 SG |
98 | */ |
99 | struct dm_i2c_chip { | |
100 | uint chip_addr; | |
101 | uint offset_len; | |
102 | uint flags; | |
85968522 | 103 | uint chip_addr_offset_mask; |
c6202d85 SG |
104 | #ifdef CONFIG_SANDBOX |
105 | struct udevice *emul; | |
182bf92d | 106 | bool test_mode; |
728d04cc | 107 | int emul_idx; |
c6202d85 SG |
108 | #endif |
109 | }; | |
110 | ||
111 | /** | |
112 | * struct dm_i2c_bus- information about an i2c bus | |
113 | * | |
114 | * An I2C bus contains 0 or more chips on it, each at its own address. The | |
115 | * bus can operate at different speeds (measured in Hz, typically 100KHz | |
116 | * or 400KHz). | |
117 | * | |
e564f054 SG |
118 | * To obtain this structure, use dev_get_uclass_priv(bus) where bus is the |
119 | * I2C bus udevice. | |
c6202d85 SG |
120 | * |
121 | * @speed_hz: Bus speed in hertz (typically 100000) | |
a40fe217 | 122 | * @max_transaction_bytes: Maximal size of single I2C transfer |
c6202d85 SG |
123 | */ |
124 | struct dm_i2c_bus { | |
125 | int speed_hz; | |
a40fe217 | 126 | int max_transaction_bytes; |
c6202d85 SG |
127 | }; |
128 | ||
7fc65bcf SG |
129 | /* |
130 | * Not all of these flags are implemented in the U-Boot API | |
131 | */ | |
132 | enum dm_i2c_msg_flags { | |
133 | I2C_M_TEN = 0x0010, /* ten-bit chip address */ | |
134 | I2C_M_RD = 0x0001, /* read data, from slave to master */ | |
135 | I2C_M_STOP = 0x8000, /* send stop after this message */ | |
136 | I2C_M_NOSTART = 0x4000, /* no start before this message */ | |
137 | I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */ | |
138 | I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */ | |
139 | I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */ | |
140 | I2C_M_RECV_LEN = 0x0400, /* length is first received byte */ | |
141 | }; | |
142 | ||
143 | /** | |
144 | * struct i2c_msg - an I2C message | |
145 | * | |
146 | * @addr: Slave address | |
147 | * @flags: Flags (see enum dm_i2c_msg_flags) | |
148 | * @len: Length of buffer in bytes, may be 0 for a probe | |
149 | * @buf: Buffer to send/receive, or NULL if no data | |
150 | */ | |
151 | struct i2c_msg { | |
152 | uint addr; | |
153 | uint flags; | |
154 | uint len; | |
155 | u8 *buf; | |
156 | }; | |
157 | ||
158 | /** | |
159 | * struct i2c_msg_list - a list of I2C messages | |
160 | * | |
161 | * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem | |
162 | * appropriate in U-Boot. | |
163 | * | |
164 | * @msg: Pointer to i2c_msg array | |
165 | * @nmsgs: Number of elements in the array | |
166 | */ | |
167 | struct i2c_msg_list { | |
168 | struct i2c_msg *msgs; | |
169 | uint nmsgs; | |
170 | }; | |
171 | ||
c6202d85 | 172 | /** |
f9a4c2da | 173 | * dm_i2c_read() - read bytes from an I2C chip |
c6202d85 SG |
174 | * |
175 | * To obtain an I2C device (called a 'chip') given the I2C bus address you | |
176 | * can use i2c_get_chip(). To obtain a bus by bus number use | |
177 | * uclass_get_device_by_seq(UCLASS_I2C, <bus number>). | |
178 | * | |
179 | * To set the address length of a devce use i2c_set_addr_len(). It | |
180 | * defaults to 1. | |
181 | * | |
182 | * @dev: Chip to read from | |
183 | * @offset: Offset within chip to start reading | |
184 | * @buffer: Place to put data | |
185 | * @len: Number of bytes to read | |
186 | * | |
185f812c | 187 | * Return: 0 on success, -ve on failure |
c6202d85 | 188 | */ |
f9a4c2da | 189 | int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len); |
c6202d85 SG |
190 | |
191 | /** | |
f9a4c2da | 192 | * dm_i2c_write() - write bytes to an I2C chip |
c6202d85 | 193 | * |
f9a4c2da | 194 | * See notes for dm_i2c_read() above. |
c6202d85 SG |
195 | * |
196 | * @dev: Chip to write to | |
197 | * @offset: Offset within chip to start writing | |
198 | * @buffer: Buffer containing data to write | |
199 | * @len: Number of bytes to write | |
200 | * | |
185f812c | 201 | * Return: 0 on success, -ve on failure |
c6202d85 | 202 | */ |
f9a4c2da SG |
203 | int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, |
204 | int len); | |
c6202d85 SG |
205 | |
206 | /** | |
f9a4c2da | 207 | * dm_i2c_probe() - probe a particular chip address |
c6202d85 SG |
208 | * |
209 | * This can be useful to check for the existence of a chip on the bus. | |
210 | * It is typically implemented by writing the chip address to the bus | |
211 | * and checking that the chip replies with an ACK. | |
212 | * | |
213 | * @bus: Bus to probe | |
214 | * @chip_addr: 7-bit address to probe (10-bit and others are not supported) | |
215 | * @chip_flags: Flags for the probe (see enum dm_i2c_chip_flags) | |
216 | * @devp: Returns the device found, or NULL if none | |
185f812c | 217 | * Return: 0 if a chip was found at that address, -ve if not |
c6202d85 | 218 | */ |
f9a4c2da SG |
219 | int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, |
220 | struct udevice **devp); | |
c6202d85 | 221 | |
ba3864f8 SG |
222 | /** |
223 | * dm_i2c_reg_read() - Read a value from an I2C register | |
224 | * | |
225 | * This reads a single value from the given address in an I2C chip | |
226 | * | |
25a0fb43 | 227 | * @dev: Device to use for transfer |
ba3864f8 | 228 | * @addr: Address to read from |
185f812c | 229 | * Return: value read, or -ve on error |
ba3864f8 SG |
230 | */ |
231 | int dm_i2c_reg_read(struct udevice *dev, uint offset); | |
232 | ||
233 | /** | |
234 | * dm_i2c_reg_write() - Write a value to an I2C register | |
235 | * | |
236 | * This writes a single value to the given address in an I2C chip | |
237 | * | |
25a0fb43 | 238 | * @dev: Device to use for transfer |
ba3864f8 SG |
239 | * @addr: Address to write to |
240 | * @val: Value to write (normally a byte) | |
185f812c | 241 | * Return: 0 on success, -ve on error |
ba3864f8 SG |
242 | */ |
243 | int dm_i2c_reg_write(struct udevice *dev, uint offset, unsigned int val); | |
244 | ||
2aefa6e3 SR |
245 | /** |
246 | * dm_i2c_reg_clrset() - Apply bitmask to an I2C register | |
247 | * | |
248 | * Read value, apply bitmask and write modified value back to the | |
249 | * given address in an I2C chip | |
250 | * | |
251 | * @dev: Device to use for transfer | |
252 | * @offset: Address for the R/W operation | |
253 | * @clr: Bitmask of bits that should be cleared | |
254 | * @set: Bitmask of bits that should be set | |
185f812c | 255 | * Return: 0 on success, -ve on error |
2aefa6e3 SR |
256 | */ |
257 | int dm_i2c_reg_clrset(struct udevice *dev, uint offset, u32 clr, u32 set); | |
258 | ||
df358c6b SG |
259 | /** |
260 | * dm_i2c_xfer() - Transfer messages over I2C | |
261 | * | |
262 | * This transfers a raw message. It is best to use dm_i2c_reg_read/write() | |
263 | * instead. | |
264 | * | |
265 | * @dev: Device to use for transfer | |
266 | * @msg: List of messages to transfer | |
267 | * @nmsgs: Number of messages to transfer | |
185f812c | 268 | * Return: 0 on success, -ve on error |
df358c6b SG |
269 | */ |
270 | int dm_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs); | |
271 | ||
c6202d85 | 272 | /** |
ca88b9b9 | 273 | * dm_i2c_set_bus_speed() - set the speed of a bus |
c6202d85 SG |
274 | * |
275 | * @bus: Bus to adjust | |
276 | * @speed: Requested speed in Hz | |
185f812c | 277 | * Return: 0 if OK, -EINVAL for invalid values |
c6202d85 | 278 | */ |
ca88b9b9 | 279 | int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed); |
c6202d85 SG |
280 | |
281 | /** | |
ca88b9b9 | 282 | * dm_i2c_get_bus_speed() - get the speed of a bus |
c6202d85 SG |
283 | * |
284 | * @bus: Bus to check | |
185f812c | 285 | * Return: speed of selected I2C bus in Hz, -ve on error |
c6202d85 | 286 | */ |
ca88b9b9 | 287 | int dm_i2c_get_bus_speed(struct udevice *bus); |
c6202d85 SG |
288 | |
289 | /** | |
290 | * i2c_set_chip_flags() - set flags for a chip | |
291 | * | |
292 | * Typically addresses are 7 bits, but for 10-bit addresses you should set | |
293 | * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing. | |
294 | * | |
295 | * @dev: Chip to adjust | |
296 | * @flags: New flags | |
185f812c | 297 | * Return: 0 if OK, -EINVAL if value is unsupported, other -ve value on error |
c6202d85 SG |
298 | */ |
299 | int i2c_set_chip_flags(struct udevice *dev, uint flags); | |
300 | ||
301 | /** | |
302 | * i2c_get_chip_flags() - get flags for a chip | |
303 | * | |
304 | * @dev: Chip to check | |
305 | * @flagsp: Place to put flags | |
185f812c | 306 | * Return: 0 if OK, other -ve value on error |
c6202d85 SG |
307 | */ |
308 | int i2c_get_chip_flags(struct udevice *dev, uint *flagsp); | |
309 | ||
310 | /** | |
311 | * i2c_set_offset_len() - set the offset length for a chip | |
312 | * | |
313 | * The offset used to access a chip may be up to 4 bytes long. Typically it | |
314 | * is only 1 byte, which is enough for chips with 256 bytes of memory or | |
315 | * registers. The default value is 1, but you can call this function to | |
316 | * change it. | |
317 | * | |
318 | * @offset_len: New offset length value (typically 1 or 2) | |
319 | */ | |
c6202d85 | 320 | int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len); |
01501804 SG |
321 | |
322 | /** | |
323 | * i2c_get_offset_len() - get the offset length for a chip | |
324 | * | |
325 | * @return: Current offset length value (typically 1 or 2) | |
326 | */ | |
327 | int i2c_get_chip_offset_len(struct udevice *dev); | |
328 | ||
85968522 RB |
329 | /** |
330 | * i2c_set_chip_addr_offset_mask() - set mask of address bits usable by offset | |
331 | * | |
332 | * Some devices listen on multiple chip addresses to achieve larger offsets | |
333 | * than their single or multiple byte offsets would allow for. You can use this | |
334 | * function to set the bits that are valid to be used for offset overflow. | |
335 | * | |
336 | * @mask: The mask to be used for high offset bits within address | |
185f812c | 337 | * Return: 0 if OK, other -ve value on error |
85968522 RB |
338 | */ |
339 | int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask); | |
340 | ||
341 | /* | |
342 | * i2c_get_chip_addr_offset_mask() - get mask of address bits usable by offset | |
343 | * | |
185f812c | 344 | * Return: current chip addr offset mask |
85968522 RB |
345 | */ |
346 | uint i2c_get_chip_addr_offset_mask(struct udevice *dev); | |
347 | ||
c6202d85 SG |
348 | /** |
349 | * i2c_deblock() - recover a bus that is in an unknown state | |
350 | * | |
351 | * See the deblock() method in 'struct dm_i2c_ops' for full information | |
352 | * | |
353 | * @bus: Bus to recover | |
185f812c | 354 | * Return: 0 if OK, -ve on error |
c6202d85 SG |
355 | */ |
356 | int i2c_deblock(struct udevice *bus); | |
357 | ||
7231522a MV |
358 | /** |
359 | * i2c_deblock_gpio_loop() - recover a bus from an unknown state by toggling SDA/SCL | |
360 | * | |
361 | * This is the inner logic used for toggling I2C SDA/SCL lines as GPIOs | |
362 | * for deblocking the I2C bus. | |
363 | * | |
364 | * @sda_pin: SDA GPIO | |
365 | * @scl_pin: SCL GPIO | |
366 | * @scl_count: Number of SCL clock cycles generated to deblock SDA | |
a1917286 | 367 | * @start_count:Number of I2C start conditions sent after deblocking SDA |
7231522a | 368 | * @delay: Delay between SCL clock line changes |
185f812c | 369 | * Return: 0 if OK, -ve on error |
7231522a MV |
370 | */ |
371 | struct gpio_desc; | |
372 | int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin, struct gpio_desc *scl_pin, | |
a1917286 MV |
373 | unsigned int scl_count, unsigned int start_count, |
374 | unsigned int delay); | |
7231522a | 375 | |
c6202d85 SG |
376 | /** |
377 | * struct dm_i2c_ops - driver operations for I2C uclass | |
378 | * | |
379 | * Drivers should support these operations unless otherwise noted. These | |
380 | * operations are intended to be used by uclass code, not directly from | |
381 | * other code. | |
382 | */ | |
383 | struct dm_i2c_ops { | |
384 | /** | |
385 | * xfer() - transfer a list of I2C messages | |
386 | * | |
387 | * @bus: Bus to read from | |
388 | * @msg: List of messages to transfer | |
389 | * @nmsgs: Number of messages in the list | |
390 | * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte, | |
391 | * -ECOMM if the speed cannot be supported, -EPROTO if the chip | |
392 | * flags cannot be supported, other -ve value on some other error | |
393 | */ | |
394 | int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs); | |
395 | ||
396 | /** | |
397 | * probe_chip() - probe for the presense of a chip address | |
398 | * | |
399 | * This function is optional. If omitted, the uclass will send a zero | |
400 | * length message instead. | |
401 | * | |
402 | * @bus: Bus to probe | |
403 | * @chip_addr: Chip address to probe | |
404 | * @chip_flags: Probe flags (enum dm_i2c_chip_flags) | |
405 | * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back | |
406 | * to default probem other -ve value on error | |
407 | */ | |
408 | int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags); | |
409 | ||
410 | /** | |
411 | * set_bus_speed() - set the speed of a bus (optional) | |
412 | * | |
413 | * The bus speed value will be updated by the uclass if this function | |
414 | * does not return an error. This method is optional - if it is not | |
415 | * provided then the driver can read the speed from | |
e564f054 | 416 | * dev_get_uclass_priv(bus)->speed_hz |
c6202d85 SG |
417 | * |
418 | * @bus: Bus to adjust | |
419 | * @speed: Requested speed in Hz | |
420 | * @return 0 if OK, -EINVAL for invalid values | |
421 | */ | |
422 | int (*set_bus_speed)(struct udevice *bus, unsigned int speed); | |
423 | ||
424 | /** | |
425 | * get_bus_speed() - get the speed of a bus (optional) | |
426 | * | |
427 | * Normally this can be provided by the uclass, but if you want your | |
428 | * driver to check the bus speed by looking at the hardware, you can | |
429 | * implement that here. This method is optional. This method would | |
e564f054 | 430 | * normally be expected to return dev_get_uclass_priv(bus)->speed_hz. |
c6202d85 SG |
431 | * |
432 | * @bus: Bus to check | |
433 | * @return speed of selected I2C bus in Hz, -ve on error | |
434 | */ | |
435 | int (*get_bus_speed)(struct udevice *bus); | |
436 | ||
437 | /** | |
438 | * set_flags() - set the flags for a chip (optional) | |
439 | * | |
440 | * This is generally implemented by the uclass, but drivers can | |
441 | * check the value to ensure that unsupported options are not used. | |
442 | * This method is optional. If provided, this method will always be | |
443 | * called when the flags change. | |
444 | * | |
445 | * @dev: Chip to adjust | |
446 | * @flags: New flags value | |
447 | * @return 0 if OK, -EINVAL if value is unsupported | |
448 | */ | |
449 | int (*set_flags)(struct udevice *dev, uint flags); | |
450 | ||
451 | /** | |
452 | * deblock() - recover a bus that is in an unknown state | |
453 | * | |
454 | * I2C is a synchronous protocol and resets of the processor in the | |
455 | * middle of an access can block the I2C Bus until a powerdown of | |
456 | * the full unit is done. This is because slaves can be stuck | |
457 | * waiting for addition bus transitions for a transaction that will | |
458 | * never complete. Resetting the I2C master does not help. The only | |
459 | * way is to force the bus through a series of transitions to make | |
460 | * sure that all slaves are done with the transaction. This method | |
461 | * performs this 'deblocking' if support by the driver. | |
462 | * | |
463 | * This method is optional. | |
464 | */ | |
465 | int (*deblock)(struct udevice *bus); | |
466 | }; | |
467 | ||
468 | #define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops) | |
469 | ||
3d1957f0 SG |
470 | /** |
471 | * struct i2c_mux_ops - operations for an I2C mux | |
472 | * | |
473 | * The current mux state is expected to be stored in the mux itself since | |
474 | * it is the only thing that knows how to make things work. The mux can | |
475 | * record the current state and then avoid switching unless it is necessary. | |
476 | * So select() can be skipped if the mux is already in the correct state. | |
477 | * Also deselect() can be made a nop if required. | |
478 | */ | |
479 | struct i2c_mux_ops { | |
480 | /** | |
481 | * select() - select one of of I2C buses attached to a mux | |
482 | * | |
483 | * This will be called when there is no bus currently selected by the | |
484 | * mux. This method does not need to deselect the old bus since | |
485 | * deselect() will be already have been called if necessary. | |
486 | * | |
487 | * @mux: Mux device | |
488 | * @bus: I2C bus to select | |
489 | * @channel: Channel number correponding to the bus to select | |
490 | * @return 0 if OK, -ve on error | |
491 | */ | |
492 | int (*select)(struct udevice *mux, struct udevice *bus, uint channel); | |
493 | ||
494 | /** | |
495 | * deselect() - select one of of I2C buses attached to a mux | |
496 | * | |
497 | * This is used to deselect the currently selected I2C bus. | |
498 | * | |
499 | * @mux: Mux device | |
500 | * @bus: I2C bus to deselect | |
501 | * @channel: Channel number correponding to the bus to deselect | |
502 | * @return 0 if OK, -ve on error | |
503 | */ | |
504 | int (*deselect)(struct udevice *mux, struct udevice *bus, uint channel); | |
505 | }; | |
506 | ||
507 | #define i2c_mux_get_ops(dev) ((struct i2c_mux_ops *)(dev)->driver->ops) | |
508 | ||
c6202d85 SG |
509 | /** |
510 | * i2c_get_chip() - get a device to use to access a chip on a bus | |
511 | * | |
512 | * This returns the device for the given chip address. The device can then | |
513 | * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc. | |
514 | * | |
515 | * @bus: Bus to examine | |
516 | * @chip_addr: Chip address for the new device | |
25ab4b03 | 517 | * @offset_len: Length of a register offset in bytes (normally 1) |
c6202d85 SG |
518 | * @devp: Returns pointer to new device if found or -ENODEV if not |
519 | * found | |
520 | */ | |
25ab4b03 SG |
521 | int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, |
522 | struct udevice **devp); | |
c6202d85 SG |
523 | |
524 | /** | |
a06728c8 SR |
525 | * i2c_get_chip_for_busnum() - get a device to use to access a chip on |
526 | * a bus number | |
c6202d85 SG |
527 | * |
528 | * This returns the device for the given chip address on a particular bus | |
529 | * number. | |
530 | * | |
531 | * @busnum: Bus number to examine | |
532 | * @chip_addr: Chip address for the new device | |
25ab4b03 | 533 | * @offset_len: Length of a register offset in bytes (normally 1) |
c6202d85 SG |
534 | * @devp: Returns pointer to new device if found or -ENODEV if not |
535 | * found | |
536 | */ | |
25ab4b03 SG |
537 | int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, |
538 | struct udevice **devp); | |
c6202d85 SG |
539 | |
540 | /** | |
d1998a9f | 541 | * i2c_chip_of_to_plat() - Decode standard I2C platform data |
c6202d85 SG |
542 | * |
543 | * This decodes the chip address from a device tree node and puts it into | |
544 | * its dm_i2c_chip structure. This should be called in your driver's | |
d1998a9f | 545 | * of_to_plat() method. |
c6202d85 SG |
546 | * |
547 | * @blob: Device tree blob | |
548 | * @node: Node offset to read from | |
549 | * @spi: Place to put the decoded information | |
550 | */ | |
d1998a9f | 551 | int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip); |
c6202d85 | 552 | |
7d7db222 SG |
553 | /** |
554 | * i2c_dump_msgs() - Dump a list of I2C messages | |
555 | * | |
556 | * This may be useful for debugging. | |
557 | * | |
558 | * @msg: Message list to dump | |
559 | * @nmsgs: Number of messages | |
560 | */ | |
561 | void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs); | |
562 | ||
b7c25b11 SG |
563 | /** |
564 | * i2c_emul_find() - Find an emulator for an i2c sandbox device | |
565 | * | |
566 | * This looks at the device's 'emul' phandle | |
567 | * | |
568 | * @dev: Device to find an emulator for | |
569 | * @emulp: Returns the associated emulator, if found * | |
185f812c | 570 | * Return: 0 if OK, -ENOENT or -ENODEV if not found |
b7c25b11 SG |
571 | */ |
572 | int i2c_emul_find(struct udevice *dev, struct udevice **emulp); | |
573 | ||
728d04cc SG |
574 | /** |
575 | * i2c_emul_set_idx() - Set the emulator index for an i2c sandbox device | |
576 | * | |
577 | * With of-platdata we cannot find the emulator using the device tree, so rely | |
578 | * on the bind() method of each i2c driver calling this function to tell us | |
579 | * the of-platdata idx of the emulator | |
580 | * | |
581 | * @dev: i2c device to set the emulator for | |
582 | * @emul_idx: of-platdata index for that emulator | |
583 | */ | |
584 | void i2c_emul_set_idx(struct udevice *dev, int emul_idx); | |
585 | ||
b7c25b11 SG |
586 | /** |
587 | * i2c_emul_get_device() - Find the device being emulated | |
588 | * | |
589 | * Given an emulator this returns the associated device | |
590 | * | |
591 | * @emul: Emulator for the device | |
185f812c | 592 | * Return: device that @emul is emulating |
b7c25b11 SG |
593 | */ |
594 | struct udevice *i2c_emul_get_device(struct udevice *emul); | |
595 | ||
fd42f263 SG |
596 | /* ACPI operations for generic I2C devices */ |
597 | extern struct acpi_ops i2c_acpi_ops; | |
598 | ||
599 | /** | |
d1998a9f | 600 | * acpi_i2c_of_to_plat() - Read properties intended for ACPI |
fd42f263 SG |
601 | * |
602 | * This reads the generic I2C properties from the device tree, so that these | |
603 | * can be used to create ACPI information for the device. | |
604 | * | |
605 | * See the i2c/generic-acpi.txt binding file for information about the | |
606 | * properties. | |
607 | * | |
608 | * @dev: I2C device to process | |
185f812c | 609 | * Return: 0 if OK, -EINVAL if acpi,hid is not present |
fd42f263 | 610 | */ |
d1998a9f | 611 | int acpi_i2c_of_to_plat(struct udevice *dev); |
fd42f263 | 612 | |
52c7e375 TR |
613 | #ifdef CONFIG_SYS_I2C_EARLY_INIT |
614 | void i2c_early_init_f(void); | |
615 | #endif | |
616 | ||
2147a169 | 617 | #if !CONFIG_IS_ENABLED(DM_I2C) |
c6202d85 | 618 | |
1f045217 WD |
619 | /* |
620 | * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING | |
621 | * | |
622 | * The implementation MUST NOT use static or global variables if the | |
623 | * I2C routines are used to read SDRAM configuration information | |
624 | * because this is done before the memories are initialized. Limited | |
625 | * use of stack-based variables are OK (the initial stack size is | |
626 | * limited). | |
627 | * | |
628 | * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING | |
629 | */ | |
630 | ||
631 | /* | |
632 | * Configuration items. | |
633 | */ | |
634 | #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ | |
635 | ||
385c9ef5 HS |
636 | #if !defined(CONFIG_SYS_I2C_MAX_HOPS) |
637 | /* no muxes used bus = i2c adapters */ | |
638 | #define CONFIG_SYS_I2C_DIRECT_BUS 1 | |
639 | #define CONFIG_SYS_I2C_MAX_HOPS 0 | |
640 | #define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) | |
79b2d0bb | 641 | #else |
385c9ef5 HS |
642 | /* we use i2c muxes */ |
643 | #undef CONFIG_SYS_I2C_DIRECT_BUS | |
79b2d0bb SR |
644 | #endif |
645 | ||
8c12045a | 646 | /* define the I2C bus number for RTC and DTT if not already done */ |
6d0f6bcf JCPV |
647 | #if !defined(CONFIG_SYS_RTC_BUS_NUM) |
648 | #define CONFIG_SYS_RTC_BUS_NUM 0 | |
8c12045a | 649 | #endif |
6d0f6bcf JCPV |
650 | #if !defined(CONFIG_SYS_SPD_BUS_NUM) |
651 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
d8a8ea5c | 652 | #endif |
8c12045a | 653 | |
385c9ef5 HS |
654 | struct i2c_adapter { |
655 | void (*init)(struct i2c_adapter *adap, int speed, | |
656 | int slaveaddr); | |
657 | int (*probe)(struct i2c_adapter *adap, uint8_t chip); | |
658 | int (*read)(struct i2c_adapter *adap, uint8_t chip, | |
659 | uint addr, int alen, uint8_t *buffer, | |
660 | int len); | |
661 | int (*write)(struct i2c_adapter *adap, uint8_t chip, | |
662 | uint addr, int alen, uint8_t *buffer, | |
663 | int len); | |
664 | uint (*set_bus_speed)(struct i2c_adapter *adap, | |
665 | uint speed); | |
666 | int speed; | |
d5243359 | 667 | int waitdelay; |
385c9ef5 HS |
668 | int slaveaddr; |
669 | int init_done; | |
670 | int hwadapnr; | |
671 | char *name; | |
672 | }; | |
673 | ||
674 | #define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ | |
675 | _set_speed, _speed, _slaveaddr, _hwadapnr, _name) \ | |
676 | { \ | |
677 | .init = _init, \ | |
678 | .probe = _probe, \ | |
679 | .read = _read, \ | |
680 | .write = _write, \ | |
681 | .set_bus_speed = _set_speed, \ | |
682 | .speed = _speed, \ | |
683 | .slaveaddr = _slaveaddr, \ | |
684 | .init_done = 0, \ | |
685 | .hwadapnr = _hwadapnr, \ | |
686 | .name = #_name \ | |
687 | }; | |
688 | ||
689 | #define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \ | |
690 | _set_speed, _speed, _slaveaddr, _hwadapnr) \ | |
691 | ll_entry_declare(struct i2c_adapter, _name, i2c) = \ | |
692 | U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \ | |
693 | _set_speed, _speed, _slaveaddr, _hwadapnr, _name); | |
694 | ||
695 | struct i2c_adapter *i2c_get_adapter(int index); | |
696 | ||
697 | #ifndef CONFIG_SYS_I2C_DIRECT_BUS | |
698 | struct i2c_mux { | |
699 | int id; | |
700 | char name[16]; | |
701 | }; | |
702 | ||
703 | struct i2c_next_hop { | |
704 | struct i2c_mux mux; | |
705 | uint8_t chip; | |
706 | uint8_t channel; | |
707 | }; | |
708 | ||
709 | struct i2c_bus_hose { | |
710 | int adapter; | |
711 | struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS]; | |
712 | }; | |
713 | #define I2C_NULL_HOP {{-1, ""}, 0, 0} | |
714 | extern struct i2c_bus_hose i2c_bus[]; | |
715 | ||
716 | #define I2C_ADAPTER(bus) i2c_bus[bus].adapter | |
717 | #else | |
718 | #define I2C_ADAPTER(bus) bus | |
719 | #endif | |
720 | #define I2C_BUS gd->cur_i2c_bus | |
721 | ||
722 | #define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus)) | |
723 | #define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus) | |
724 | #define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) | |
725 | ||
726 | #ifndef CONFIG_SYS_I2C_DIRECT_BUS | |
727 | #define I2C_MUX_PCA9540_ID 1 | |
728 | #define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"} | |
729 | #define I2C_MUX_PCA9542_ID 2 | |
730 | #define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"} | |
731 | #define I2C_MUX_PCA9544_ID 3 | |
732 | #define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"} | |
733 | #define I2C_MUX_PCA9547_ID 4 | |
734 | #define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"} | |
e6658749 MB |
735 | #define I2C_MUX_PCA9548_ID 5 |
736 | #define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"} | |
385c9ef5 HS |
737 | #endif |
738 | ||
98aed379 | 739 | #ifndef I2C_SOFT_DECLARATIONS |
2eb48ff7 | 740 | # if (defined(CONFIG_AT91RM9200) || \ |
0cf0b931 | 741 | defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ |
cb96a0a4 | 742 | defined(CONFIG_AT91SAM9263)) |
78132275 | 743 | # define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; |
98aed379 HS |
744 | # else |
745 | # define I2C_SOFT_DECLARATIONS | |
746 | # endif | |
747 | #endif | |
ecf5f077 | 748 | |
1f045217 WD |
749 | /* |
750 | * Initialization, must be called once on start up, may be called | |
751 | * repeatedly to change the speed and slave addresses. | |
752 | */ | |
753 | void i2c_init(int speed, int slaveaddr); | |
06d01dbe | 754 | void i2c_init_board(void); |
1f045217 | 755 | |
55dabcc8 | 756 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) |
385c9ef5 HS |
757 | /* |
758 | * i2c_get_bus_num: | |
759 | * | |
760 | * Returns index of currently active I2C bus. Zero-based. | |
761 | */ | |
762 | unsigned int i2c_get_bus_num(void); | |
763 | ||
764 | /* | |
765 | * i2c_set_bus_num: | |
766 | * | |
767 | * Change the active I2C bus. Subsequent read/write calls will | |
768 | * go to this one. | |
769 | * | |
770 | * bus - bus index, zero based | |
771 | * | |
772 | * Returns: 0 on success, not 0 on failure | |
773 | * | |
774 | */ | |
775 | int i2c_set_bus_num(unsigned int bus); | |
776 | ||
777 | /* | |
778 | * i2c_init_all(): | |
779 | * | |
780 | * Initializes all I2C adapters in the system. All i2c_adap structures must | |
781 | * be initialized beforehead with function pointers and data, including | |
782 | * speed and slaveaddr. Returns 0 on success, non-0 on failure. | |
783 | */ | |
784 | void i2c_init_all(void); | |
785 | ||
786 | /* | |
787 | * Probe the given I2C chip address. Returns 0 if a chip responded, | |
788 | * not 0 on failure. | |
789 | */ | |
790 | int i2c_probe(uint8_t chip); | |
791 | ||
792 | /* | |
793 | * Read/Write interface: | |
794 | * chip: I2C chip address, range 0..127 | |
795 | * addr: Memory (register) address within the chip | |
796 | * alen: Number of bytes to use for addr (typically 1, 2 for larger | |
797 | * memories, 0 for register type devices with only one | |
798 | * register) | |
799 | * buffer: Where to read/write the data | |
800 | * len: How many bytes to read/write | |
801 | * | |
802 | * Returns: 0 on success, not 0 on failure | |
803 | */ | |
804 | int i2c_read(uint8_t chip, unsigned int addr, int alen, | |
805 | uint8_t *buffer, int len); | |
806 | ||
807 | int i2c_write(uint8_t chip, unsigned int addr, int alen, | |
808 | uint8_t *buffer, int len); | |
809 | ||
810 | /* | |
811 | * Utility routines to read/write registers. | |
812 | */ | |
813 | uint8_t i2c_reg_read(uint8_t addr, uint8_t reg); | |
814 | ||
815 | void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val); | |
816 | ||
817 | /* | |
818 | * i2c_set_bus_speed: | |
819 | * | |
820 | * Change the speed of the active I2C bus | |
821 | * | |
822 | * speed - bus speed in Hz | |
823 | * | |
824 | * Returns: new bus speed | |
825 | * | |
826 | */ | |
827 | unsigned int i2c_set_bus_speed(unsigned int speed); | |
67b23a32 | 828 | |
385c9ef5 HS |
829 | /* |
830 | * i2c_get_bus_speed: | |
831 | * | |
832 | * Returns speed of currently active I2C bus in Hz | |
833 | */ | |
67b23a32 | 834 | |
385c9ef5 | 835 | unsigned int i2c_get_bus_speed(void); |
67b23a32 | 836 | |
385c9ef5 | 837 | #else |
67b23a32 | 838 | |
1f045217 WD |
839 | /* |
840 | * Probe the given I2C chip address. Returns 0 if a chip responded, | |
841 | * not 0 on failure. | |
842 | */ | |
843 | int i2c_probe(uchar chip); | |
844 | ||
845 | /* | |
846 | * Read/Write interface: | |
847 | * chip: I2C chip address, range 0..127 | |
848 | * addr: Memory (register) address within the chip | |
849 | * alen: Number of bytes to use for addr (typically 1, 2 for larger | |
850 | * memories, 0 for register type devices with only one | |
851 | * register) | |
852 | * buffer: Where to read/write the data | |
853 | * len: How many bytes to read/write | |
854 | * | |
855 | * Returns: 0 on success, not 0 on failure | |
856 | */ | |
857 | int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); | |
858 | int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); | |
859 | ||
860 | /* | |
861 | * Utility routines to read/write registers. | |
862 | */ | |
ecf5f077 TT |
863 | static inline u8 i2c_reg_read(u8 addr, u8 reg) |
864 | { | |
865 | u8 buf; | |
866 | ||
ecf5f077 TT |
867 | #ifdef DEBUG |
868 | printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); | |
869 | #endif | |
870 | ||
ecf5f077 | 871 | i2c_read(addr, reg, 1, &buf, 1); |
ecf5f077 TT |
872 | |
873 | return buf; | |
874 | } | |
875 | ||
876 | static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) | |
877 | { | |
ecf5f077 TT |
878 | #ifdef DEBUG |
879 | printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", | |
880 | __func__, addr, reg, val); | |
881 | #endif | |
882 | ||
ecf5f077 | 883 | i2c_write(addr, reg, 1, &val, 1); |
ecf5f077 | 884 | } |
1f045217 | 885 | |
bb99ad6d BW |
886 | /* |
887 | * Functions for setting the current I2C bus and its speed | |
888 | */ | |
889 | ||
890 | /* | |
891 | * i2c_set_bus_num: | |
892 | * | |
893 | * Change the active I2C bus. Subsequent read/write calls will | |
894 | * go to this one. | |
895 | * | |
53677ef1 | 896 | * bus - bus index, zero based |
bb99ad6d | 897 | * |
53677ef1 | 898 | * Returns: 0 on success, not 0 on failure |
bb99ad6d BW |
899 | * |
900 | */ | |
9ca880a2 | 901 | int i2c_set_bus_num(unsigned int bus); |
bb99ad6d BW |
902 | |
903 | /* | |
904 | * i2c_get_bus_num: | |
905 | * | |
906 | * Returns index of currently active I2C bus. Zero-based. | |
907 | */ | |
908 | ||
9ca880a2 | 909 | unsigned int i2c_get_bus_num(void); |
bb99ad6d BW |
910 | |
911 | /* | |
912 | * i2c_set_bus_speed: | |
913 | * | |
914 | * Change the speed of the active I2C bus | |
915 | * | |
53677ef1 | 916 | * speed - bus speed in Hz |
bb99ad6d | 917 | * |
53677ef1 | 918 | * Returns: 0 on success, not 0 on failure |
bb99ad6d BW |
919 | * |
920 | */ | |
9ca880a2 | 921 | int i2c_set_bus_speed(unsigned int); |
bb99ad6d BW |
922 | |
923 | /* | |
924 | * i2c_get_bus_speed: | |
925 | * | |
926 | * Returns speed of currently active I2C bus in Hz | |
927 | */ | |
928 | ||
9ca880a2 | 929 | unsigned int i2c_get_bus_speed(void); |
69d9eda4 | 930 | #endif /* CONFIG_SYS_I2C_LEGACY */ |
385c9ef5 HS |
931 | |
932 | /* | |
933 | * only for backwardcompatibility, should go away if we switched | |
934 | * completely to new multibus support. | |
935 | */ | |
55dabcc8 | 936 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) |
385c9ef5 HS |
937 | # if !defined(CONFIG_SYS_MAX_I2C_BUS) |
938 | # define CONFIG_SYS_MAX_I2C_BUS 2 | |
939 | # endif | |
ea0f73ab | 940 | # define I2C_MULTI_BUS 1 |
385c9ef5 HS |
941 | #else |
942 | # define CONFIG_SYS_MAX_I2C_BUS 1 | |
943 | # define I2C_MULTI_BUS 0 | |
944 | #endif | |
bb99ad6d | 945 | |
cd7b4e82 MV |
946 | /* NOTE: These two functions MUST be always_inline to avoid code growth! */ |
947 | static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); | |
948 | static inline unsigned int I2C_GET_BUS(void) | |
949 | { | |
950 | return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; | |
951 | } | |
952 | ||
953 | static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); | |
954 | static inline void I2C_SET_BUS(unsigned int bus) | |
955 | { | |
956 | if (I2C_MULTI_BUS) | |
957 | i2c_set_bus_num(bus); | |
958 | } | |
959 | ||
7ca8f73a ŁM |
960 | /* Multi I2C definitions */ |
961 | enum { | |
962 | I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7, | |
963 | I2C_8, I2C_9, I2C_10, | |
964 | }; | |
965 | ||
a9d2ae70 RS |
966 | /** |
967 | * Get FDT values for i2c bus. | |
968 | * | |
969 | * @param blob Device tree blbo | |
185f812c | 970 | * Return: the number of I2C bus |
a9d2ae70 RS |
971 | */ |
972 | void board_i2c_init(const void *blob); | |
973 | ||
974 | /** | |
975 | * Find the I2C bus number by given a FDT I2C node. | |
976 | * | |
977 | * @param blob Device tree blbo | |
978 | * @param node FDT I2C node to find | |
185f812c | 979 | * Return: the number of I2C bus (zero based), or -1 on error |
a9d2ae70 RS |
980 | */ |
981 | int i2c_get_bus_num_fdt(int node); | |
982 | ||
983 | /** | |
984 | * Reset the I2C bus represented by the given a FDT I2C node. | |
985 | * | |
986 | * @param blob Device tree blbo | |
987 | * @param node FDT I2C node to find | |
185f812c | 988 | * Return: 0 if port was reset, -1 if not found |
a9d2ae70 RS |
989 | */ |
990 | int i2c_reset_port_fdt(const void *blob, int node); | |
c6202d85 SG |
991 | |
992 | #endif /* !CONFIG_DM_I2C */ | |
993 | ||
1f045217 | 994 | #endif /* _I2C_H_ */ |