[u-boot.git] / drivers / net / dwc_eth_qos_rockchip.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright Contributors to the U-Boot project.
 *
 * rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
 *
 * Ported code is intentionally left as close as possible with linux counter
 * part in order to simplify future porting of fixes and support for other SoCs.
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <net.h>
#include <phy.h>
#include <regmap.h>
#include <reset.h>
#include <syscon.h>
#include <asm/gpio.h>
#include <linux/delay.h>

#include "dwc_eth_qos.h"

struct rk_gmac_ops {
	const char *compatible;
	int (*set_to_rgmii)(struct udevice *dev,
			    int tx_delay, int rx_delay);
	int (*set_to_rmii)(struct udevice *dev);
	int (*set_gmac_speed)(struct udevice *dev);
	void (*set_clock_selection)(struct udevice *dev, bool enable);
	u32 regs[3];
};

struct rockchip_platform_data {
	struct reset_ctl_bulk resets;
	const struct rk_gmac_ops *ops;
	int id;
	bool clock_input;
	struct regmap *grf;
	struct regmap *php_grf;
};

#define HIWORD_UPDATE(val, mask, shift) \
		((val) << (shift) | (mask) << ((shift) + 16))

#define GRF_BIT(nr)	(BIT(nr) | BIT((nr) + 16))
#define GRF_CLR_BIT(nr)	(BIT((nr) + 16))

#define RK3568_GRF_GMAC0_CON0		0x0380
#define RK3568_GRF_GMAC0_CON1		0x0384
#define RK3568_GRF_GMAC1_CON0		0x0388
#define RK3568_GRF_GMAC1_CON1		0x038c

/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
#define RK3568_GMAC_PHY_INTF_SEL_RGMII	\
		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
#define RK3568_GMAC_PHY_INTF_SEL_RMII	\
		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
#define RK3568_GMAC_FLOW_CTRL			GRF_BIT(3)
#define RK3568_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(3)
#define RK3568_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
#define RK3568_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(1)
#define RK3568_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
#define RK3568_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)

/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
#define RK3568_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
#define RK3568_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)

static int rk3568_set_to_rgmii(struct udevice *dev,
			       int tx_delay, int rx_delay)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 con0, con1;

	con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
				 RK3568_GRF_GMAC0_CON0;
	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
				 RK3568_GRF_GMAC0_CON1;

	regmap_write(data->grf, con0,
		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));

	regmap_write(data->grf, con1,
		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
		     RK3568_GMAC_RXCLK_DLY_ENABLE |
		     RK3568_GMAC_TXCLK_DLY_ENABLE);

	return 0;
}

static int rk3568_set_to_rmii(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 con1;

	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
				 RK3568_GRF_GMAC0_CON1;
	regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);

	return 0;
}

static int rk3568_set_gmac_speed(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	ulong rate;
	int ret;

	switch (eqos->phy->speed) {
	case SPEED_10:
		rate = 2500000;
		break;
	case SPEED_100:
		rate = 25000000;
		break;
	case SPEED_1000:
		rate = 125000000;
		break;
	default:
		return -EINVAL;
	}

	ret = clk_set_rate(&eqos->clk_tx, rate);
	if (ret < 0)
		return ret;

	return 0;
}

/* sys_grf */
#define RK3588_GRF_GMAC_CON7			0x031c
#define RK3588_GRF_GMAC_CON8			0x0320
#define RK3588_GRF_GMAC_CON9			0x0324

#define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)
#define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)
#define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)
#define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)

#define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
#define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)

/* php_grf */
#define RK3588_GRF_GMAC_CON0			0x0008
#define RK3588_GRF_CLK_CON1			0x0070

#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\
	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
#define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\
	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))

#define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))
#define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))

#define RK3588_GMAC_CLK_SELET_CRU(id)		GRF_BIT(5 * (id) + 4)
#define RK3588_GMAC_CLK_SELET_IO(id)		GRF_CLR_BIT(5 * (id) + 4)

#define RK3588_GMAC_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)
#define RK3588_GMAC_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)

#define RK3588_GMAC_CLK_RGMII_DIV1(id)		\
			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
#define RK3588_GMAC_CLK_RGMII_DIV5(id)		\
			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
#define RK3588_GMAC_CLK_RGMII_DIV50(id)		\
			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))

#define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)
#define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)

static int rk3588_set_to_rgmii(struct udevice *dev,
			       int tx_delay, int rx_delay)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 offset_con, id = data->id;

	offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :
				     RK3588_GRF_GMAC_CON8;

	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
		     RK3588_GMAC_CLK_RGMII_MODE(id));

	regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
		     RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
		     RK3588_GMAC_TXCLK_DLY_ENABLE(id));

	regmap_write(data->grf, offset_con,
		     RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
		     RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));

	return 0;
}

static int rk3588_set_to_rmii(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
		     RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
		     RK3588_GMAC_CLK_RMII_MODE(data->id));

	return 0;
}

static int rk3588_set_gmac_speed(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	u32 val = 0, id = data->id;

	switch (eqos->phy->speed) {
	case SPEED_10:
		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
			val = RK3588_GMAC_CLK_RMII_DIV20(id);
		else
			val = RK3588_GMAC_CLK_RGMII_DIV50(id);
		break;
	case SPEED_100:
		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
			val = RK3588_GMAC_CLK_RMII_DIV2(id);
		else
			val = RK3588_GMAC_CLK_RGMII_DIV5(id);
		break;
	case SPEED_1000:
		if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
			val = RK3588_GMAC_CLK_RGMII_DIV1(id);
		else
			return -EINVAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);

	return 0;
}

static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :
				      RK3588_GMAC_CLK_SELET_CRU(data->id);

	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :
			RK3588_GMAC_CLK_RMII_GATE(data->id);

	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
}

static const struct rk_gmac_ops rk_gmac_ops[] = {
	{
		.compatible = "rockchip,rk3568-gmac",
		.set_to_rgmii = rk3568_set_to_rgmii,
		.set_to_rmii = rk3568_set_to_rmii,
		.set_gmac_speed = rk3568_set_gmac_speed,
		.regs = {
			0xfe2a0000, /* gmac0 */
			0xfe010000, /* gmac1 */
			0x0, /* sentinel */
		},
	},
	{
		.compatible = "rockchip,rk3588-gmac",
		.set_to_rgmii = rk3588_set_to_rgmii,
		.set_to_rmii = rk3588_set_to_rmii,
		.set_gmac_speed = rk3588_set_gmac_speed,
		.set_clock_selection = rk3588_set_clock_selection,
		.regs = {
			0xfe1b0000, /* gmac0 */
			0xfe1c0000, /* gmac1 */
			0x0, /* sentinel */
		},
	},
	{ }
};

static const struct rk_gmac_ops *get_rk_gmac_ops(struct udevice *dev)
{
	const struct rk_gmac_ops *ops = rk_gmac_ops;

	while (ops->compatible) {
		if (device_is_compatible(dev, ops->compatible))
			return ops;
		ops++;
	}

	return NULL;
}

static int eqos_probe_resources_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data;
	const char *clock_in_out;
	int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
	int ret;

	data = calloc(1, sizeof(struct rockchip_platform_data));
	if (!data)
		return -ENOMEM;

	data->ops = get_rk_gmac_ops(dev);
	if (!data->ops) {
		ret = -EINVAL;
		goto err_free;
	}

	for (int i = 0; data->ops->regs[i]; i++) {
		if (data->ops->regs[i] == (u32)eqos->regs) {
			data->id = i;
			break;
		}
	}

	pdata->priv_pdata = data;
	pdata->phy_interface = eqos->config->interface(dev);
	pdata->max_speed = eqos->max_speed;

	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
		pr_err("Invalid PHY interface\n");
		ret = -EINVAL;
		goto err_free;
	}

	data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
	if (IS_ERR(data->grf)) {
		dev_err(dev, "Missing rockchip,grf property\n");
		ret = -EINVAL;
		goto err_free;
	}

	if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
		data->php_grf =
			syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
		if (IS_ERR(data->php_grf)) {
			dev_err(dev, "Missing rockchip,php-grf property\n");
			ret = -EINVAL;
			goto err_free;
		}
	}

	ret = reset_get_bulk(dev, &data->resets);
	if (ret < 0)
		goto err_free;

	reset_assert_bulk(&data->resets);

	ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
	if (ret) {
		dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
		goto err_release_resets;
	}

	if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {
		ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
		if (ret) {
			dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
			goto err_release_resets;
		}
	}

	clock_in_out = dev_read_string(dev, "clock_in_out");
	if (clock_in_out && !strcmp(clock_in_out, "input"))
		data->clock_input = true;
	else
		data->clock_input = false;

	/* snps,reset props are deprecated, do bare minimum to support them */
	if (dev_read_bool(dev, "snps,reset-active-low"))
		reset_flags |= GPIOD_ACTIVE_LOW;

	dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);

	gpio_request_by_name(dev, "snps,reset-gpio", 0,
			     &eqos->phy_reset_gpio, reset_flags);

	return 0;

err_release_resets:
	reset_release_bulk(&data->resets);
err_free:
	free(data);

	return ret;
}

static int eqos_remove_resources_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
		dm_gpio_free(dev, &eqos->phy_reset_gpio);

	reset_release_bulk(&data->resets);
	free(data);

	return 0;
}

static int eqos_stop_resets_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	return reset_assert_bulk(&data->resets);
}

static int eqos_start_resets_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	return reset_deassert_bulk(&data->resets);
}

static int eqos_stop_clks_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	if (data->ops->set_clock_selection)
		data->ops->set_clock_selection(dev, false);

	return 0;
}

static int eqos_start_clks_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;
	int tx_delay, rx_delay, ret;

	if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
		udelay(eqos->reset_delays[1]);

		ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
		if (ret < 0)
			return ret;

		udelay(eqos->reset_delays[2]);
	}

	if (data->ops->set_clock_selection)
		data->ops->set_clock_selection(dev, true);

	tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
	rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);

	switch (pdata->phy_interface) {
	case PHY_INTERFACE_MODE_RGMII:
		return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
	case PHY_INTERFACE_MODE_RGMII_ID:
		return data->ops->set_to_rgmii(dev, 0, 0);
	case PHY_INTERFACE_MODE_RGMII_RXID:
		return data->ops->set_to_rgmii(dev, tx_delay, 0);
	case PHY_INTERFACE_MODE_RGMII_TXID:
		return data->ops->set_to_rgmii(dev, 0, rx_delay);
	case PHY_INTERFACE_MODE_RMII:
		return data->ops->set_to_rmii(dev);
	}

	return -EINVAL;
}

static int eqos_set_tx_clk_speed_rk(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct rockchip_platform_data *data = pdata->priv_pdata;

	return data->ops->set_gmac_speed(dev);
}

static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev)
{
	struct eqos_priv *eqos = dev_get_priv(dev);

	return clk_get_rate(&eqos->clk_master_bus);
}

static struct eqos_ops eqos_rockchip_ops = {
	.eqos_inval_desc = eqos_inval_desc_generic,
	.eqos_flush_desc = eqos_flush_desc_generic,
	.eqos_inval_buffer = eqos_inval_buffer_generic,
	.eqos_flush_buffer = eqos_flush_buffer_generic,
	.eqos_probe_resources = eqos_probe_resources_rk,
	.eqos_remove_resources = eqos_remove_resources_rk,
	.eqos_stop_resets = eqos_stop_resets_rk,
	.eqos_start_resets = eqos_start_resets_rk,
	.eqos_stop_clks = eqos_stop_clks_rk,
	.eqos_start_clks = eqos_start_clks_rk,
	.eqos_calibrate_pads = eqos_null_ops,
	.eqos_disable_calibration = eqos_null_ops,
	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
	.eqos_get_enetaddr = eqos_null_ops,
	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
};

struct eqos_config eqos_rockchip_config = {
	.reg_access_always_ok = false,
	.mdio_wait = 10,
	.swr_wait = 50,
	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
	.axi_bus_width = EQOS_AXI_WIDTH_64,
	.interface = dev_read_phy_mode,
	.ops = &eqos_rockchip_ops,
};
Commit	Line	Data
8e76ff61 JK	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Copyright Contributors to the U-Boot project.
	4	*
	5	* rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
	6	*
	7	* Ported code is intentionally left as close as possible with linux counter
	8	* part in order to simplify future porting of fixes and support for other SoCs.
	9	*/
	10
d678a59d	11	#include <common.h>
8e76ff61 JK	12	#include <clk.h>
	13	#include <dm.h>
	14	#include <dm/device_compat.h>
	15	#include <net.h>
	16	#include <phy.h>
	17	#include <regmap.h>
	18	#include <reset.h>
	19	#include <syscon.h>
	20	#include <asm/gpio.h>
	21	#include <linux/delay.h>
	22
	23	#include "dwc_eth_qos.h"
	24
	25	struct rk_gmac_ops {
	26	const char *compatible;
	27	int (set_to_rgmii)(struct udevice dev,
	28	int tx_delay, int rx_delay);
	29	int (set_to_rmii)(struct udevice dev);
	30	int (set_gmac_speed)(struct udevice dev);
01b8ed47	31	void (set_clock_selection)(struct udevice dev, bool enable);
8e76ff61 JK	32	u32 regs[3];
	33	};
	34
	35	struct rockchip_platform_data {
	36	struct reset_ctl_bulk resets;
	37	const struct rk_gmac_ops *ops;
	38	int id;
01b8ed47	39	bool clock_input;
8e76ff61	40	struct regmap *grf;
01b8ed47	41	struct regmap *php_grf;
8e76ff61 JK	42	};
	43
	44	#define HIWORD_UPDATE(val, mask, shift) \
	45	((val) << (shift) \| (mask) << ((shift) + 16))
	46
	47	#define GRF_BIT(nr) (BIT(nr) \| BIT((nr) + 16))
	48	#define GRF_CLR_BIT(nr) (BIT((nr) + 16))
	49
	50	#define RK3568_GRF_GMAC0_CON0 0x0380
	51	#define RK3568_GRF_GMAC0_CON1 0x0384
	52	#define RK3568_GRF_GMAC1_CON0 0x0388
	53	#define RK3568_GRF_GMAC1_CON1 0x038c
	54
	55	/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
	56	#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
	57	(GRF_BIT(4) \| GRF_CLR_BIT(5) \| GRF_CLR_BIT(6))
	58	#define RK3568_GMAC_PHY_INTF_SEL_RMII \
	59	(GRF_CLR_BIT(4) \| GRF_CLR_BIT(5) \| GRF_BIT(6))
	60	#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
	61	#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
	62	#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
	63	#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
	64	#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
	65	#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
	66
	67	/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
	68	#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
	69	#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
	70
	71	static int rk3568_set_to_rgmii(struct udevice *dev,
	72	int tx_delay, int rx_delay)
	73	{
	74	struct eth_pdata *pdata = dev_get_plat(dev);
	75	struct rockchip_platform_data *data = pdata->priv_pdata;
	76	u32 con0, con1;
	77
	78	con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
	79	RK3568_GRF_GMAC0_CON0;
	80	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
	81	RK3568_GRF_GMAC0_CON1;
	82
	83	regmap_write(data->grf, con0,
	84	RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) \|
	85	RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
	86
	87	regmap_write(data->grf, con1,
	88	RK3568_GMAC_PHY_INTF_SEL_RGMII \|
	89	RK3568_GMAC_RXCLK_DLY_ENABLE \|
	90	RK3568_GMAC_TXCLK_DLY_ENABLE);
	91
	92	return 0;
	93	}
	94
	95	static int rk3568_set_to_rmii(struct udevice *dev)
	96	{
	97	struct eth_pdata *pdata = dev_get_plat(dev);
	98	struct rockchip_platform_data *data = pdata->priv_pdata;
	99	u32 con1;
	100
	101	con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
	102	RK3568_GRF_GMAC0_CON1;
	103	regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
	104
	105	return 0;
106	}
107
108	static int rk3568_set_gmac_speed(struct udevice *dev)
109	{
110	struct eqos_priv *eqos = dev_get_priv(dev);
111	ulong rate;
112	int ret;
113
114	switch (eqos->phy->speed) {
115	case SPEED_10:
116	rate = 2500000;
117	break;
118	case SPEED_100:
119	rate = 25000000;
120	break;
121	case SPEED_1000:
122	rate = 125000000;
123	break;
124	default:
125	return -EINVAL;
126	}
127
128	ret = clk_set_rate(&eqos->clk_tx, rate);
129	if (ret < 0)
130	return ret;
131
132	return 0;
133	}
134
01b8ed47 JK	135	/* sys_grf */
	136	#define RK3588_GRF_GMAC_CON7 0x031c
	137	#define RK3588_GRF_GMAC_CON8 0x0320
	138	#define RK3588_GRF_GMAC_CON9 0x0324
	139
	140	#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
	141	#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
	142	#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
	143	#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
	144
	145	#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
	146	#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
	147
	148	/* php_grf */
	149	#define RK3588_GRF_GMAC_CON0 0x0008
	150	#define RK3588_GRF_CLK_CON1 0x0070
	151
	152	#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
	153	(GRF_BIT(3 + (id) * 6) \| GRF_CLR_BIT(4 + (id) * 6) \| GRF_CLR_BIT(5 + (id) * 6))
	154	#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
	155	(GRF_CLR_BIT(3 + (id) * 6) \| GRF_CLR_BIT(4 + (id) * 6) \| GRF_BIT(5 + (id) * 6))
	156
	157	#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
	158	#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
	159
	160	#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4)
	161	#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)
	162
	163	#define RK3588_GMAC_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
	164	#define RK3588_GMAC_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
	165
	166	#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
	167	(GRF_CLR_BIT(5 * (id) + 2) \| GRF_CLR_BIT(5 * (id) + 3))
	168	#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
	169	(GRF_BIT(5 * (id) + 2) \| GRF_BIT(5 * (id) + 3))
	170	#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
	171	(GRF_CLR_BIT(5 * (id) + 2) \| GRF_BIT(5 * (id) + 3))
	172
	173	#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
	174	#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
	175
	176	static int rk3588_set_to_rgmii(struct udevice *dev,
	177	int tx_delay, int rx_delay)
	178	{
	179	struct eth_pdata *pdata = dev_get_plat(dev);
	180	struct rockchip_platform_data *data = pdata->priv_pdata;
	181	u32 offset_con, id = data->id;
	182
	183	offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :
	184	RK3588_GRF_GMAC_CON8;
	185
	186	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
	187	RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
	188
	189	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
	190	RK3588_GMAC_CLK_RGMII_MODE(id));
	191
	192	regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
	193	RK3588_GMAC_RXCLK_DLY_ENABLE(id) \|
	194	RK3588_GMAC_TXCLK_DLY_ENABLE(id));
	195
	196	regmap_write(data->grf, offset_con,
	197	RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) \|
	198	RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
199
200	return 0;
201	}
202
203	static int rk3588_set_to_rmii(struct udevice *dev)
204	{
205	struct eth_pdata *pdata = dev_get_plat(dev);
206	struct rockchip_platform_data *data = pdata->priv_pdata;
207
208	regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
209	RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));
210
211	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
212	RK3588_GMAC_CLK_RMII_MODE(data->id));
213
214	return 0;
215	}
216
217	static int rk3588_set_gmac_speed(struct udevice *dev)
218	{
219	struct eqos_priv *eqos = dev_get_priv(dev);
220	struct eth_pdata *pdata = dev_get_plat(dev);
221	struct rockchip_platform_data *data = pdata->priv_pdata;
222	u32 val = 0, id = data->id;
223
224	switch (eqos->phy->speed) {
225	case SPEED_10:
226	if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
227	val = RK3588_GMAC_CLK_RMII_DIV20(id);
228	else
229	val = RK3588_GMAC_CLK_RGMII_DIV50(id);
230	break;
231	case SPEED_100:
232	if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
233	val = RK3588_GMAC_CLK_RMII_DIV2(id);
234	else
235	val = RK3588_GMAC_CLK_RGMII_DIV5(id);
236	break;
237	case SPEED_1000:
238	if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
239	val = RK3588_GMAC_CLK_RGMII_DIV1(id);
240	else
241	return -EINVAL;
242	break;
243	default:
244	return -EINVAL;
245	}
246
247	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
248
249	return 0;
250	}
251
252	static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
253	{
254	struct eth_pdata *pdata = dev_get_plat(dev);
255	struct rockchip_platform_data *data = pdata->priv_pdata;
256
257	u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :
258	RK3588_GMAC_CLK_SELET_CRU(data->id);
259
260	val \|= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :
261	RK3588_GMAC_CLK_RMII_GATE(data->id);
262
263	regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
264	}
265
8e76ff61 JK	266	static const struct rk_gmac_ops rk_gmac_ops[] = {
	267	{
	268	.compatible = "rockchip,rk3568-gmac",
	269	.set_to_rgmii = rk3568_set_to_rgmii,
	270	.set_to_rmii = rk3568_set_to_rmii,
	271	.set_gmac_speed = rk3568_set_gmac_speed,
	272	.regs = {
	273	0xfe2a0000, /* gmac0 */
	274	0xfe010000, /* gmac1 */
	275	0x0, /* sentinel */
	276	},
	277	},
01b8ed47 JK	278	{
	279	.compatible = "rockchip,rk3588-gmac",
	280	.set_to_rgmii = rk3588_set_to_rgmii,
	281	.set_to_rmii = rk3588_set_to_rmii,
	282	.set_gmac_speed = rk3588_set_gmac_speed,
	283	.set_clock_selection = rk3588_set_clock_selection,
	284	.regs = {
	285	0xfe1b0000, /* gmac0 */
	286	0xfe1c0000, /* gmac1 */
	287	0x0, /* sentinel */
	288	},
	289	},
8e76ff61 JK	290	{ }
	291	};
	292
	293	static const struct rk_gmac_ops get_rk_gmac_ops(struct udevice dev)
	294	{
	295	const struct rk_gmac_ops *ops = rk_gmac_ops;
	296
	297	while (ops->compatible) {
	298	if (device_is_compatible(dev, ops->compatible))
	299	return ops;
	300	ops++;
	301	}
	302
	303	return NULL;
	304	}
	305
	306	static int eqos_probe_resources_rk(struct udevice *dev)
	307	{
	308	struct eqos_priv *eqos = dev_get_priv(dev);
	309	struct eth_pdata *pdata = dev_get_plat(dev);
	310	struct rockchip_platform_data *data;
01b8ed47	311	const char *clock_in_out;
8e76ff61 JK	312	int reset_flags = GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE;
	313	int ret;
	314
	315	data = calloc(1, sizeof(struct rockchip_platform_data));
	316	if (!data)
	317	return -ENOMEM;
	318
	319	data->ops = get_rk_gmac_ops(dev);
	320	if (!data->ops) {
	321	ret = -EINVAL;
	322	goto err_free;
	323	}
	324
	325	for (int i = 0; data->ops->regs[i]; i++) {
	326	if (data->ops->regs[i] == (u32)eqos->regs) {
	327	data->id = i;
	328	break;
	329	}
	330	}
	331
	332	pdata->priv_pdata = data;
	333	pdata->phy_interface = eqos->config->interface(dev);
	334	pdata->max_speed = eqos->max_speed;
	335
	336	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
	337	pr_err("Invalid PHY interface\n");
	338	ret = -EINVAL;
	339	goto err_free;
	340	}
	341
	342	data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
	343	if (IS_ERR(data->grf)) {
	344	dev_err(dev, "Missing rockchip,grf property\n");
	345	ret = -EINVAL;
	346	goto err_free;
	347	}
	348
01b8ed47 JK	349	if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
	350	data->php_grf =
	351	syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
	352	if (IS_ERR(data->php_grf)) {
	353	dev_err(dev, "Missing rockchip,php-grf property\n");
	354	ret = -EINVAL;
	355	goto err_free;
	356	}
	357	}
	358
8e76ff61 JK	359	ret = reset_get_bulk(dev, &data->resets);
	360	if (ret < 0)
	361	goto err_free;
	362
	363	reset_assert_bulk(&data->resets);
	364
	365	ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
	366	if (ret) {
	367	dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
	368	goto err_release_resets;
	369	}
	370
01b8ed47 JK	371	if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {
	372	ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
	373	if (ret) {
	374	dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
c9309f40	375	goto err_release_resets;
01b8ed47	376	}
8e76ff61 JK	377	}
8e76ff61 JK	378
01b8ed47 JK	379	clock_in_out = dev_read_string(dev, "clock_in_out");
	380	if (clock_in_out && !strcmp(clock_in_out, "input"))
	381	data->clock_input = true;
	382	else
	383	data->clock_input = false;
	384
8e76ff61 JK	385	/* snps,reset props are deprecated, do bare minimum to support them */
	386	if (dev_read_bool(dev, "snps,reset-active-low"))
	387	reset_flags \|= GPIOD_ACTIVE_LOW;
	388
	389	dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);
	390
	391	gpio_request_by_name(dev, "snps,reset-gpio", 0,
	392	&eqos->phy_reset_gpio, reset_flags);
	393
	394	return 0;
	395
8e76ff61 JK	396	err_release_resets:
	397	reset_release_bulk(&data->resets);
	398	err_free:
	399	free(data);
	400
	401	return ret;
	402	}
	403
	404	static int eqos_remove_resources_rk(struct udevice *dev)
	405	{
	406	struct eqos_priv *eqos = dev_get_priv(dev);
	407	struct eth_pdata *pdata = dev_get_plat(dev);
	408	struct rockchip_platform_data *data = pdata->priv_pdata;
	409
	410	if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
	411	dm_gpio_free(dev, &eqos->phy_reset_gpio);
	412
8e76ff61 JK	413	reset_release_bulk(&data->resets);
	414	free(data);
	415
	416	return 0;
	417	}
	418
	419	static int eqos_stop_resets_rk(struct udevice *dev)
	420	{
	421	struct eth_pdata *pdata = dev_get_plat(dev);
	422	struct rockchip_platform_data *data = pdata->priv_pdata;
	423
	424	return reset_assert_bulk(&data->resets);
	425	}
	426
	427	static int eqos_start_resets_rk(struct udevice *dev)
	428	{
	429	struct eth_pdata *pdata = dev_get_plat(dev);
	430	struct rockchip_platform_data *data = pdata->priv_pdata;
	431
	432	return reset_deassert_bulk(&data->resets);
	433	}
	434
	435	static int eqos_stop_clks_rk(struct udevice *dev)
	436	{
01b8ed47 JK	437	struct eth_pdata *pdata = dev_get_plat(dev);
	438	struct rockchip_platform_data *data = pdata->priv_pdata;
	439
	440	if (data->ops->set_clock_selection)
	441	data->ops->set_clock_selection(dev, false);
	442
8e76ff61 JK	443	return 0;
	444	}
	445
	446	static int eqos_start_clks_rk(struct udevice *dev)
	447	{
	448	struct eqos_priv *eqos = dev_get_priv(dev);
	449	struct eth_pdata *pdata = dev_get_plat(dev);
	450	struct rockchip_platform_data *data = pdata->priv_pdata;
	451	int tx_delay, rx_delay, ret;
	452
	453	if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
	454	udelay(eqos->reset_delays[1]);
	455
	456	ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
	457	if (ret < 0)
	458	return ret;
	459
	460	udelay(eqos->reset_delays[2]);
	461	}
	462
01b8ed47 JK	463	if (data->ops->set_clock_selection)
	464	data->ops->set_clock_selection(dev, true);
	465
8e76ff61 JK	466	tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
	467	rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);
	468
	469	switch (pdata->phy_interface) {
	470	case PHY_INTERFACE_MODE_RGMII:
	471	return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
	472	case PHY_INTERFACE_MODE_RGMII_ID:
	473	return data->ops->set_to_rgmii(dev, 0, 0);
	474	case PHY_INTERFACE_MODE_RGMII_RXID:
	475	return data->ops->set_to_rgmii(dev, tx_delay, 0);
	476	case PHY_INTERFACE_MODE_RGMII_TXID:
	477	return data->ops->set_to_rgmii(dev, 0, rx_delay);
	478	case PHY_INTERFACE_MODE_RMII:
	479	return data->ops->set_to_rmii(dev);
	480	}
	481
	482	return -EINVAL;
	483	}
	484
	485	static int eqos_set_tx_clk_speed_rk(struct udevice *dev)
	486	{
	487	struct eth_pdata *pdata = dev_get_plat(dev);
	488	struct rockchip_platform_data *data = pdata->priv_pdata;
	489
	490	return data->ops->set_gmac_speed(dev);
	491	}
	492
	493	static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev)
	494	{
	495	struct eqos_priv *eqos = dev_get_priv(dev);
	496
	497	return clk_get_rate(&eqos->clk_master_bus);
	498	}
	499
	500	static struct eqos_ops eqos_rockchip_ops = {
	501	.eqos_inval_desc = eqos_inval_desc_generic,
	502	.eqos_flush_desc = eqos_flush_desc_generic,
	503	.eqos_inval_buffer = eqos_inval_buffer_generic,
	504	.eqos_flush_buffer = eqos_flush_buffer_generic,
	505	.eqos_probe_resources = eqos_probe_resources_rk,
	506	.eqos_remove_resources = eqos_remove_resources_rk,
	507	.eqos_stop_resets = eqos_stop_resets_rk,
	508	.eqos_start_resets = eqos_start_resets_rk,
	509	.eqos_stop_clks = eqos_stop_clks_rk,
	510	.eqos_start_clks = eqos_start_clks_rk,
	511	.eqos_calibrate_pads = eqos_null_ops,
	512	.eqos_disable_calibration = eqos_null_ops,
	513	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
	514	.eqos_get_enetaddr = eqos_null_ops,
	515	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
	516	};
	517
	518	struct eqos_config eqos_rockchip_config = {
	519	.reg_access_always_ok = false,
	520	.mdio_wait = 10,
	521	.swr_wait = 50,
	522	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
	523	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
	524	.axi_bus_width = EQOS_AXI_WIDTH_64,
	525	.interface = dev_read_phy_mode,
	526	.ops = &eqos_rockchip_ops,
	527	};